Student: Omkar Bhilare
Mentors: Michael Welling
GSoC: GSoC entry
This project is currently just a proposal.
Completed All the requirements listed on the ideas page.
The PR request for cross-compilation task: #154.
IRC: Omkar Bhilare
School: Veermata Jijabai Technological Institute
Primary language : English, Hindi, Marathi
Typical work hours: 10AM-8PM Indian Standard Time
Previous GSoC participation: This is my first time applying for GSoC, I'm an Electronics enthusiast and have a great interest in fields like FPGA, Digital VLSI, Computer Architecture. I have experienced with Intel's Quartus, Xilinx's vivado, and opensource toolchains for ice40. I have also done many projects related to Cyclone2, Upduino3.0(ICE40), Sipeed Tang Primer FPGA.
About your project
Project name: Beaglewire Software Support
The BeagleWire is an FPGA development platform that has been designed for use with BeagleBone boards. BeagleWire is a cape on which there is an FPGA device (Lattice iCE40HX). The software support for BeagleWire is still in the development phase. In this project, I'm developing and testing the existing software support of Beaglewire.
The known primary issue in Beaglewire is the interface between 32MB SDRAM and ICE40HX4K. For this Solution, I'm going to try options like LiteDRAM(a small footprint and configurable DRAM core) or Advanced SDRAM controller provided by LATTICE.
- Why LiteDRAM for SDRAM Control
The Core produced by LiteDRAM is
1. Fully pipelined, high performance.
2. Configurable commands depth on bankmachines.
4. Periodic refresh/ZQ short calibration (up to 8 postponed refreshes).
- LiteDRAM is already used in commercial and open-source designs
- Testing and Improvement of Subsystem Like I2C, SPI, PWM, UART
In this project I'm going to test all the subsystems like I2C, SPI, PWM, UART in Hardware and the primary goal will be to debug the issues related to it and fix them accordingly. Along with the driver code ready to use solutions will be added in software support.
- I2C: There are two grove Connectors on BeagleWire for I2C, I will test the current Verilog Code of I2C in hardware, and will found out if further improvements can be done or not.
- UART: The existing code of Uart will be tested in hardware, and few examples also will be added for UART.
- PWM: New Example will be created for testing of PWM. Servo Code will serve the purpose of testing the PWM drivers.
- There are current Issues open on BeagleWire Repository, These will be solved during this project.
- More PMODs will be interfaced with the BeagleWire.
- Increase the Documentation and also add getting started guide for BeagleWire.
Details of Implementation
- First of all, I need to load a pre-prepared BBB image to beagle with existing all required drivers and scripts to start BeagleWire development.
The steps give on Quick Start Guide:
$ wget https://rcn-ee.net/rootfs/bb.org/testing/BeagleWire/BeagleWire-image.tar.xz
$ sha256sum BeagleWire-image.tar.xz eb862b8898b821627909952854688b46b93778fff4164c7c096453025ec7caeb
Unpack image and write the image to the memory card (please check if you have the correct SD card device — in my case it is /dev/sdd):
$ tar xf BeagleWire-image.tar.xz $ sudo dd if=image.img of=/dev/sdX
- To generate the bitstream I'm going to first try the existing fpga-load script which leverages the FPGA manager, which is the core which exports a set of functions for programming an FPGA with an Image.
Provide a development timeline with a milestone each of the 11 weeks and any pre-work. (A realistic timeline is critical to our selection process.)
|Mar 30||Proposal complete, Submitted to https://summerofcode.withgoogle.com|
|Apr 27||Proposal accepted or rejected|
|May 18||Pre-work complete, Coding officially begins!|
|May 25||Milestone #1, Introductory YouTube video|
|June 1||Milestone #2|
|June 8||Milestone #3|
|June 15 18:00 UTC||Milestone #4, Mentors and students can begin submitting Phase 1 evaluations|
|June 19 18:00 UTC||Phase 1 Evaluation deadline|
|June 22||Milestone #5|
|June 29||Milestone #6|
|July 6||Milestone #7|
|July 13 18:00 UTC||Milestone #8, Mentors and students can begin submitting Phase 2 evaluations|
|July 17 18:00 UTC||Phase 2 Evaluation deadline|
|July 20||Milestone #9|
|July 27||Milestone #10|
|August 3||Milestone #11, Completion YouTube video|
|August 10 - 17 18:00 UTC||Final week: Students submit their final work product and their final mentor evaluation|
|August 17 - 24 18:00 UTC||Mentors submit final student evaluations|
Experience and approach
In 5-15 sentences, convince us you will be able to successfully complete your project in the timeline you have described.
What will you do if you get stuck on your project and your mentor isn’t around?
If successfully completed, what will its impact be on the BeagleBoard.org community? Include quotes from BeagleBoard.org community members who can be found on http://beagleboard.org/discuss and http://bbb.io/gsocchat.
Please complete the requirements listed on the ideas page. Provide link to pull request.
Is there anything else we should have asked you?