BeagleBone Power Management
Work in progress: plan is to first collect the raw info, then organize and add prose.
|BBone White (TPS65217B)||BBone Black (TPS65217C)|
|LDO1||1.8 V||100 mA||vrtc||LDO1||1.8 V||100 mA||vrtc|
|DCDC1||1.8 V||1200 mA||ddr2||DCDC1||1.35 V||1200 mA||ddr3l|
|1v8||LDO3||1.8 V||400 mA||1v8|
|LDO2||3.3 V||100 mA||power led||LDO2||3.3 V||100 mA||power led|
|LDO3||3.3 V||200 mA||3v3a||LDO3||3.3 V||400 mA||3v3a|
|LDO4||3.3 V||200 mA||3v3b||U4||3.3 V||500 mA||3v3b|
|U8||3.3 V||1000 mA||3v3exp||3v3exp|
|DCDC2||1.285 V||1200 mA||vdd_mpu||DCDC2||1.325 V||1200 mA||vdd_mpu|
|DCDC3||1.125 V||1200 mA||vdd_core||DCDC3||1.125 V||1200 mA||vdd_core|
Hardware is a BBB rev C patched to have a unified 3v3 rail, no external connections other than power, probes, and console cable.
Two kernels are compared: the one on the right is a standard kernel + device tree which enables the (reset-insensitive) HDMI framer, while the one on the left leaves the HDMI framer in standby (its default state, negligible power consumption). There are other differences, but those should be irrelevant during shutdown, certainly once power-on reset is asserted (PGOOD low).
Most current consumption is eliminated at the start of the powerdown sequence when PGOOD goes low, although there's a brief burst shortly afterwards (no idea why). Current ramps down more 2 ms later when the core and mpu supplies are disabled, and drops to negligible once the 3v3 supply is cut. Current temporarily increases again due to VDDS leakage until it too is cut.
When the HDMI framer is enabled, its continued current consumption (until 1v8 is cut) is clearly visible.
Clean shutdown (while powered via DC plug):
Same thing, but with the power path being cut by the PMIC at the start of the powerdown sequence, the BeagleBone is now running off its capacitors. In this case it managed to make it without losing regulation at any point, but only barely so. With the HDMI framer enabled (image forthcoming) the 3v3 and 1v8 supplies receive a premature dent.
The PMIC tries, it really does. In fact, while the 3.3V supplies can't be saved (obviously, with the SYS capacitors charged at a mere 3.4V or so), when not burdened by the HDMI framer it still has 2.4V on SYS by the time the 3v3 is disabled, so it almost certainly would have maintained regulation on the remaining supplies if it weren't for the VDDS leakage.
By the time the PMIC intervenes the 3v3 supply has already lost regulation, and it clearly makes no attempt to sequence the remaining supplies but disables them simultaneously. The HDMI kernel actually initially has a gentler slope since that kernel happens to have better power management. The inexplicable sudden steepening of slope that happens there is worrying.