Beagleboard gsoc 2019 bi-directional progress

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Revision as of 13:51, 16 July 2019 by Pranav083 (talk | contribs) (Date : 10 July 2019)
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About Me

IRC: pranav_kumar
Github: https://github.com/pranav083
E-Linux Username: pranav083
School: UIET,Panjab University,Chandigarh
Country: India
Primary language: English,Hindi
Typical work hours: 9:30 - 23:00 IST GMT/EST/PST to Adjusted Time
Previous GSoC participation: This is my first time participation in gsoc .I got intrested for it by seeing the vast amount of development for open source hardware around the world .And i also want to become a part of it.
Skills: C,Python,ROS,OpenCV,Embeddded C,Electronics Prototying,circuit designing

Tools(proficient): Git, Linux, C

Experience: C, Python, OpenCV, Arduino

Hardware Skills: Raspberry Pi, ICs, Circuit Designing, Atmel chips, I2C, circuit designing, circuit debugging.

Reference Design For A GPIO-based Parallel Bi-Directional Bus

Project name: Reference Design For A GPIO-based Parallel Bi-Directional Bus

Student: Pranav Kumar
Mentors: Andrew Henderson, Kumar Abhishek, Hunyue Yau
Code: https://github.com/pranav083/pocket_beagle-work
Wiki: https://elinux.org/index.php?title=/BeagleBoard/GSoC/GPIO-parallel-bi-dir-bus
Youtube Playlist: https://www.youtube.com/playlist?list=PLttoix_9Us2yHM4zNr08ynm4iwXZTgxam

Important sites

Part A:

  • Command explanation for converting device tree in readable format:
https://stackoverflow.com/questions/36090929/modifying-the-device-tree-for-the-beaglebone-black
  • A get start guide:
https://zeekhuge.me/post/a_handfull_of_commands_and_scripts_to_get_started_with_beagleboneblack/
  • Outdated but fine source on pru:
https://www.element14.com/community/community/designcenter/single-board-computers/next-gen_beaglebone//blog/2013/05/22/bbb--working-with-the-pru-icssprussv2
  • A basic guide to pru programming:
https://markayoder.github.io/PRUCookbook/
  • A online to understand kernel structure of beaglebone on the device tree:
http://git.ti.com/ti-linux-kernel/ti-linux-3-8-y-kernel/trees/master/arch/arm/boot/dts

Part B:

  • For using the prussdrv technique in pru programming through asssembly language:
https://github.com/hendersa/bes through you have to make couple of changes to get it working.
  • basic PRU example :
https://www.ofitselfso.com/BBBCSIO/Help/BBBCSIOHelp_PRUBlinkUSR3LEDExamplePASMCode.html
  • pin P8 header:
http://exploringbeaglebone.com/wp-content/uploads/resources/BBBP8Header.png
  • pin P9 header :
http://exploringbeaglebone.com/wp-content/uploads/resources/BBBP9Header.png
  • for undersading gpio functionality :
https://credentiality2.blogspot.com/2015/09/beaglebone-pru-gpio-example.html
  • pru pin modes register etc. :
https://elinux.org/Ti_AM33XX_PRUSSv2#Beaglebone_PRU_connections_and_modes
  • Function use while compiling through prussdrv technique:
http://processors.wiki.ti.com/index.php/PRU_Linux_Application_Loader_API_Guide#prussdrv_exec_program
  • learning vim with ease :
https://www.openvim.com/

Part C:

https://github.com/jadonk/validation-scripts/tree/master/test-capemgr
  • device tree generation :
https://www.kilobaser.com/blog/2014-07-28-beaglebone-black-devicetreeoverlay-generator
  • Easy Go through example on device tree(usart pins):
https://learn.adafruit.com/introduction-to-the-beaglebone-black-device-tree/device-tree-overlays

Part D:

Sites with error

  • error404:
https://github.com/beagleboard/kernel/tree/4.1 

reference from page https://elinux.org/Capemgr

  • device tree generator
https://www.kilobaser.com/blog/2014-07-28-beaglebone-black-devicetreeoverlay-generator

Common Commannd

  • To decompile the device tree blob(/boot/dtbs/4.11.xx):
sudo dtc -I dtb -O dts -o am335x-boneblack.dts am335x-boneblack.dtb
  • To recompile the device tree(/boot/dtbs/4.11.xx):
sudo dtc -I dts -O dtb -o file.dtb file.dts
  • To compile dtbo file(/lib/firmware/):
sudo dtc -O dtb -o file.dtbo -b 0 -@ file.dts
  • To complile a normal pasm code (assembly code) :
sudo pasm -b file.p 

It will generate a file.bin file in the same directory

  • To compile it using pruss technique :
 sudo arm-linux-gnueabihf-g++ pru.cpp prussdrv.c -o file_out

For the above given file go to the given repository https://github.com/pranav083/pocket_beagle-work/tree/master/pru
Note: Always remember to make changes in the device tree file located in /lib/firmware/ directory

  • Run the program by the following command
sudo ./file_out 

(reference from the above file output)

Basic Guide on how to upload code to PRU in BeagleBone

  • Assuming that you are running beaglebone os with the kernel version 4.14.xx version (mine kernel version during the time of test is 4.14.71-ti-r80 ). Or you can check the kernel version through the following command by runnning into the terminal on beaglebone connected through the ssh window:
debian@beaglebone:~$ uname -r

Note: Ignore the $ sign while copying the command

  • Note: Should have a working internet connection while doing this either in your computer or in beagle board. If using the internet connection on the desktop then use the scp protocol to perform the copy operation from your pc to the beagleboard. like :
username@ideapad:~/scp file_name debian@192.162.7.2:~/

or if you have a folder to copy then

username@ideapad:~/scp -r folder_name debian@192.162.7.2:~/  
  • Download the busybox package from the ti site listed as ( ARM-A8 Installer for PRU CGT ) the latest version of the file :
https://www.ti.com/tool/download/PRU-CGT-2-3 

and after that run the following command to install the package :

debian@beaglebone:~$ sudo ./ti_cgt_pru_2.3.2_armlinuxa8hf_busybox_installer.sh 

that was the the latest version in my case.

  • Clone the following git repository into the beagleboard :
https://github.com/beagleboard/am335x_pru_package

Run the following command in the directory

sudo make
sudo make install
  • now to check for the validation of the installation run :
debian@beaglebone:~$ pasm

and it should run without any error

  • Clone this repository into your beaglebone :
https://github.com/pranav083/pru_prussdrv/


Now the main installation part of the guide is completed.
In this repo(given above) you will find several files some with the extension .dts , .p , .c , .cpp , .h and .o where:

Extension  Description 
.cpp       c++ program File  
.c         c program File  
.p         pru assembly code file 
.h         header file
.o         object file
.dts       device tree file

Now do the following steps to put the device tree file in the following directory:

 debian@beaglebone:~$ cd ~/pru_prussdrv/
 debian@beaglebone:~$ sudo cp PRU-GPIO-EXAMPLE2.dts  /lib/firmware/

To edit the device tree file:

 debian@beaglebone:~$ sudo vim /lib/firmware/PRU-GPIO-EXAMPLE2.dts

To compile the device tree file:

 debian@beaglebone:~$ sudo dtc -O dtb -o /lib/firmware/PRU-GPIO-EXAMPLE2.dtbo -b 0 -@ /lib/firmware/PRU-GPIO-EXAMPLE2.dts

Now ,reboot the Beagle Bone Black to update the device tree file:

 debian@beaglebone:~$ sudo reboot


  • Note : Updating is Device tree File is an important step. Every time you make changes on the pin like accessing it in different modes it is necessary to update the device tree file ,compile it and reboot the device.

Now to compile the assembly code (.p or .pasm) extension file, <filename> any reference file e.g, p8_11.p or p8_11.pasm :

debian@beaglebone:~$ cd pru_prussdrv/  
debian@beaglebone:~$ sudo pasm -b <filename>.p

It will generate a <filename>.bin (binary file) , which you have to put in the pru.cpp file (file in the cloned repo.) at line no. 93 inside the file, Replace the file name as:

Line No. 93: prussdrv_exec_program (PRU_NUM, "./<filename>.bin");

Compile the file to generate an exectuable file:

debian@beaglebone:~$ sudo arm-linux-gnueabihf-g++ pru.cpp prussdrv.c -o <filename>_out -w

It have following components as :

command                   Description     
sudo                      access as superuser   
arm-linux-gnueabihf-g++   c++ Compiler for arm
pru.cpp                   reference file  
prussdrv.c                supported file for the above file
-o                        outfile    
<filename>_out            outfile name 
-w                        ignore any warning

It will generate a exectuable file named <filename>_out , To run it:

debian@beaglebone:~$ sudo ./<filename>_out 

If everything goes right. Then, you will be able to see the output.

Beaglebone Black connections and modes of shift register 74HC595

  • Note : All the connection must pass through the logic level converter as Beagle Bone Black support 3.3v logic level and shift register support the logic level of 5v .Otherwise , it will damage the board.
  • If using "TXS0108E High-Speed Full Duplex 8 Channel Logic Level Converter".Then, At the enable pin connect a 10K ohm resistance with the 3.3v power supply as it is not mention anywhere and it will simply not work.
Sl. No. IC 74HC595 Pins IC 74HC595 Pins Name pin Mode state Pinmux Mode BB Header BB Pin Name GPIO No. Offset reg DT offset DT pinmux
1 1 QB OUTPUT
2 2 QC OUTPUT
3 3 QD OUTPUT
4 4 QE OUTPUT
5 5 QF OUTPUT
6 6 QG OUTPUT
7 7 QH OUTPUT
8 8 GND
9 9 QH ' DATA(to next IC)
10 10 SRCLR HIGH (active state) Mode_7 P8_11 GPIO1_13 45 834h 0x034 0x007
11 11 SRCLK LATCH PIN Mode_7 P8_12 GPIO1_12 44 830h 0x030 0x007
12 12 RCLK CLOCK PIN Mode_7 P8_15 GPIO1_15 47 88ch 0x03c 0x007
13 13 OE LOW(active state) Mode_7 P8_13 GPIO0_23 23 824h 0x024 0x007
14 14 SER DATA PIN Mode_7 P8_16 GPIO1_14 46 838h 0x038 0x007
15 15 Q A OUTPUT
16 16 VCC

shift_register reference from : https://www.ti.com/lit/ds/symlink/sn74hc595.pdf

Beaglebone Black connections and modes of shift register 74HC299

  • Note : All the connection must pass through the logic level converter as Beagle Bone Black support 3.3v logic level and shift register support the logic level of 5v .Otherwise , it will damage the board.
  • If using "TXS0108E High-Speed Full Duplex 8 Channel Logic Level Converter".Then, At the enable pin connect a 10K ohm resistance with the 3.3v power supply as it is not mention anywhere and it will simply not work.

Connection with the first shift register 74hc299 on which the logic analyzer is connected as because according to its datasheet its pins supports very less current on its I/O Pins. In this mode the pin be in given mode of s0 and s1

Sl. No. IC 74HC299 Pins IC 74HC299 Pins Name pin Mode state Pinmux Mode BB Header BB Pin Name GPIO No. Offset reg DT offset DT pinmux
1 1 S0 MODE STATE(high) Mode_7 P8_11 GPIO1_13 45 834h 0x034 0x007
2 2 OE1 LOW(active state)
3 3 OE2 LOW(active state)
4 4 I/O 6 OUTPUT
5 5 I/O 4 OUTPUT
6 6 I/O 2 OUTPUT
7 7 I/O 0 OUTPUT
8 8 Q0 Data to next ic(left shift)
9 9 MR(reset) HIGH(active state)
10 10 GND
11 11 DS0 Data input(Right Shift) Mode_7 P8_3 GPIO1_6 38 818h 0x018 0x007
12 12 CP CLOCK PULSE Mode_7 P8_16 GPIO1_14 46 838h 0x038 0x007
13 13 I/O 1 OUTPUT
14 14 I/O 3 OUTPUT
15 15 I/O 5 OUTPUT
16 16 I/O 7 OUTPUT
17 17 Q 7 Data to next ic(right shift)
18 18 DS 7
19 19 S1 MODE STATE(low) Mode_7 P8_12 GPIO1_12 44 830h 0x030 0x007
20 20 VCC

Connection with the cascaded second shift register 74hc299 on which the toggle switch as input pins on its I/O Pins. In this mode the pin be in given mode of s0 and s1 given below.

Sl. No. IC 74HC299 Pins IC 74HC299 Pins Name pin Mode state Pinmux Mode BB Header BB Pin Name GPIO No. Offset reg DT offset DT pinmux
1 1 S0 MODE STATE(high) Mode_7 P8_11 GPIO1_13 45 834h 0x034 0x007
2 2 OE1 LOW(active state)
3 3 OE2 LOW(active state)
4 4 I/O 6 INPUT
5 5 I/O 4 INPUT
6 6 I/O 2 INPUT
7 7 I/O 0 INPUT
8 8 Q0 Data to next ic(left shift)
9 9 MR(reset) HIGH(active state)
10 10 GND
11 11 DS0 Data input(Right Shift) input from previous Q7 of 74hc299
12 12 CP CLOCK PULSE Mode_7 P8_16 GPIO1_14 46 838h 0x038 0x007
13 13 I/O 1 INPUT
14 14 I/O 3 INPUT
15 15 I/O 5 INPUT
16 16 I/O 7 INPUT
17 17 Q 7 Data to BB Black Mode_7(input mode) P8_4 GPIO1_7 38 81ch 0x01c 0x027
18 18 DS 7
19 19 S1 MODE STATE(High) Mode_7 P8_12 GPIO1_12 44 830h 0x030 0x007
20 20 VCC


The working mode for this shift register must assign the given

S1 S0 Modes
0  0  No Change
0  1  Shift Left
1  0  Shift Right
1  1  Parallel Load


Datasheet reference from the site:

http://www.ti.com/lit/ds/symlink/cd74hc299.pdf

and

https://assets.nexperia.com/documents/data-sheet/74HC299.pdf

Daily progress :

Date : 31 May 2019

  • First I made an introductory youtube video of my project
  • Purchased hardware related to this project like 8-bit logic analyzer ,logic level converter
  • Understand about the code structure on making kernel module Beagleboard and understanding the beaglelogic code docs
  • Read a little bit about kernel module development from this page .

Date : 1 June 2019

  • Till now made the circuit based on the GitHub link with shift register circuit diagram.
  • Made the circuit for testing the board see the circuit drive link
  • Further work is to implement first user space program then PRU assembly code program.
  • completed studying kernel module development from site as suggested by my mentor and further looking into makefile

Date : 2 June 2019

I think i should also include blocker and goals in my further work

  • Till Now
    • Today I studied more about kernel module development and try to understand the code base starting from docs, then kernel folder and firmware folder
    • Try to complete the first week commitment of making the video for the different interfacing circuit but faces some problem due to less understanding assembly code in PRU
    • As i was working earlier in the User space so i was comfortable to make the program their but i want to submit the video and code with the assembly code
  • Blockers:
    • During navigating through the code of beaglelogic .asm file are less understandable for me .
    • Less understaning of the PRU assembly code to tackle that i watched again pru video from beagle bone site.
    • came across a github page during my search for barebone pru programming on pocket_beagle_samples
    • And downloaded the Sitara PRU but it was too big to be understable to me.

Date : 3 June 2019

  • Blocker
    • Building the program was not successful send my issue to my mentor
    • reading the datasheet stated above but very less success with it

Date : 4 June 2019

  • Till Now
    • while waiting for the response from the mentors started to study the assembly guide as found from different websites
    • completed the video training course on the pru programming and its different aspects through : https://training.ti.com/PRU-training-series
    • Setup ccs studio in a hope for running the pru through assembly codes
  • Blocker :
    • Still exploring the right way to program the pru in the beagle bone
    • Compile the code with out the main function and got bus error
    • Though found a way program as stated on most of the sites through the ti ccs studio but it is not the right way to continue

Date : 5 June 2019

  • Till Now
    • Got reply from the mentor and it worked after including main function and by compiling
    • starting every thing from new by re flashing the os image on the beaglebone black wireless
    • unable to install the library from the site : https://github.com/beagleboard/am335x_pru_package
    • Today is the meeting day and led a little discussion on which approach to use prussdrv or remoteproc.
  • Blocker
    • Still dont know how to get the system working through the assembly code and then come through the setup guide of complier form
    • Tried the method again of enabling pru from element14 site

As the project progress a little bit i thing of writing a blog on enabling pru in beagle board as the most of the sources are outdated

Date : 6 June 2019

  • Till Now
    • Changed the uEnv.txt for enabling remotproc pru system in beaglebone
    • Today finally get the pru assembly code working most of thanks to @hendersa guidance
    • Because till now from my side i had searched most of the resources that i can avail from web, beaglebone google group,etc.
    • But learn many things about its working and structure in the mean time .
  • Blocker
    • Most of the earlier problrm that i was facing is over for now now testing to run assembly code.

Date : 7 June 2019

Date : 8 June 2019

Date : 9 June 2019

  • Till Now
    • reading out the device tree and resource table generation
    • updated the done work on my github (through for this time it is very less :( .)
    • I was getting problem in navigating through vim .so,i Practice it from https://www.openvim.com (as i also dont know the commands)
  • Blocker
    • still not able to activate the gpio present in the p8 and p9 header through the assembly code
    • submitted my query to the mentors waiting for the reply

Date : 10 June 2019

  • Till Now
    • checking for the different techinique available for activating the gpio and as the resources available are a bit old so i have to find out resources from different place to make it work
    • digging deep into the datasheet in understanding the how the pins are getting activated through the pasm code
  • Blocker
    • same as above still no success on acquiring the pins

Date : 11 June 2019

  • Till Now
    • the mail received by the refernce to the derek molloy lecture in which he taught about the device tree understanding, compiling.
    • but it was for the kernel 3.8 and their is no folder named
/sys/devices/bone_capemgr.*/slots 

in the recent kernel version

  • Blocker
    • able to change the file but the effect are visible on the board

Date : 12-13 June 2019

  • Till Now
    • some how able to change and understand how the device tree work and the procedure to activate according to the previous kernel
    • But to eliminate any error of possibility i shifted to beaglebone black Rev C .As many site give their preference to change the device tree located in the folder /file
/boot/dtbs/4.14.71-ti-r80/am335x-boneblack.dts 

and changing the file gives no effect on the board .so, to eliminate any error of possibility i shifted to the Black Rev C .As given in the guide http://www.ofitselfso.com/BeagleNotes/AboutTheDeviceTree.pdf

    • Repeat the example that studied earlier in hope that pru pins start working
    • not much work done in this day other than this.

Date : 14 June 2019

  • Till Now
    • while searching on the internet came acrooss a code which seems to be working. Through it doesnot have documentation but it is understandable excepts for few code https://gist.github.com/jianingy/b144c9f70ae059a734fe5d49cb99cd30
    • for the first time i was able to activate the gpio no p8_13 by under stand the code. And the few thing that i learnt that
   lbco r0, CPRUCFG, 4, 4   // read SYSCFG
   clr  r0.t4               // clear SYSCFG[STANDBY_INIT]
   sbco r0, CPRUCFG, 4, 4   // enable OCP master port;
  1. first enable ocp master port mode a
  2. then make changes to device tree in according to that
  3. make the output enable for the pin
  • Blocker
    • still not able to understand the following line on the above link (line 43,53)
SET r30, r30, 15
CLR r30, r30, 15 

- as r30 register means it is an output register in which their is no listing of p8_13 port if i take the reference from the page : https://elinux.org/Ti_AM33XX_PRUSSv2#Beaglebone_PRU_connections_and_modes - and if go through the command it means that it is manipulating P8_15 as given in the table. But the P8_13 pin is activated not that pin p8_15 which should be activated according the reference information

  • Blocker
    • To test these code started to make my own set of activated pins in the device tree in the folder
/lib/firmware

Date : 15 June 2019

  • Till Now
    • making the device tree for the program but the problem is that pin available from the pru is scatted as pins are their but some give functionality of both input and output is less.
    • https://gist.github.com/pranav083/263142be5e0480025b2f7cd2a78ed631 here is the done work till now
    • Note: the above stated pins are now for demonstration reference purpose only. Just testing the derek molloy style of activating the ports of pru through the device tree.
    • But the problem that still remains that how the p8_15 will activated as previous day guide shows that p8_13 can be controlled with register r30 and bit no. 15.
    • made a little commit to my working directory on github.
  • Blocker
    • will raise the concern with my mentor about this and the project is going on slow speed i want to make the things a little bit fast.

Date : 16 June 2019

  • Till Now
    • My previous problem got solved regarding the p8_13 header pins. Its came out that the pin available is basically memory mapped and their is no need of line 43 and 53 as stated in the page link https://gist.github.com/jianingy/b144c9f70ae059a734fe5d49cb99cd30 listed on 14 june 2019 on the.
    • Able to create devive tree file (*.dtbo) and also able to make changes in according that in the assembly code mainly working on the mode 7 of pin for now.hc
    • Now finally working on making assembly code for swift register 74hc595 now.

Date : 17-18 June 2019

Date : 19 June 2019

  • Till Now
    • As told by @ds2 made the table of pin that i had used in the during the working of shift register 74hc595. Through he did not recommend using mode 7 of the board as it is directly connected the ARM processor
    • Some suggestion is given by @abhishek_ on the pin mux and device tree overlay file
    • regarding wave(timing) of register diagram its is suggested by @hendersa to use https://wavedrom.com
  • blocker
    • still not clear how to move further running the suggestion given by @abhishek still no success on accessing the pins using the pru
    • their is confussion regarding the device tree overlay to me i think.

Date : 20 June 2019

Date : 21 June 2019

  • Till Now
    • As said by @ds2 said to dig more into the datasheet of am335xx link :https://elinux.org/images/6/65/Spruh73c.pdf. Thanks to him able to find a lot of information regardingg the PRU in the datsheet.
    • Also suggested by @Abhishek_ about the pinmux tools of Texas Instrument: https://dev.ti.com
    • Studied the Device tree formation of from ti pinmux tool . Tested on the the Board But it does not seems to compile and again try testing on the different pins on the board.
  • Blockers

Date : 22-23 June 2019

  • Till Now
    • As @hendersa and @abhishek_ told me during the kernel development of the project to look into the Beagle logic project which have some important information regarding my project.
    • Especially, In the link: https://github.com/abhishek-kakkar/BeagleLogic in the folder kernel and firmware, Studied that and compare that with the datasheet of am3335xx for a better understanding.
    • Got a mail received from @hendersa regarding the progress of the project. He provided the link to play with regarding the kernel source development: https://github.com/RobertCNelson/dtb-rebuilder

Date : 24-26 June 2019

  • Till Now
    • in this point of time i was not able to understand what to do next. so, i started to read the documentation and little bit about the kernel module development , i have less understanding of kernel modules till now
    • pointed and listed out the important topic related to the programming of pru and its memory structure

Date : 27 June 2019

  • Till Now
    • studied how to give input to the register and its memory mapping into the pru
    • got a mail about the shift register today and will be shipped by tomorrow

Date : 28 June 2019

  • Till Now
    • Today finally i got the shift register on which i have to work upon the delivery was though at the evening ,so first thing first reading the datasheet and get to run it on a easy prototype board like arduino
    • making the wiring of the circuit with arduino and testing its different modes of operation by testing through the logic analyzer as the output signal provided by ic 74hc299 is quite according to the datasheet
  • Blockers
    • the max operating frequency is 50 MHz only for CMOS version of 74hc299 which is the newer version
    • It does not support the latching of the data as it available in 74hc595 swift registers

Date : 29 June 2019

  • Till Now
    • made the cascaded circuit of the shift registers 74hc299 as i am going to use as both input and output using the same circuit with one single assembly program that can be controlled using the beagle bone black (it was complex circuit to build it on the breadboard as it require many components and lots of jumper wire )
    • I had made the code but does not seems to be working , i started to debug the code , datasheet to get solution so then i decided to make the program splits in the smaller parts
  • Blocker
    • shift register work not done completely

Date : 30 June 2019

  • Till Now
    • as first check the shift register 74hc299 with beagle bone black
    • then interface some toggle switch and led to have a controlled output through the data stored in the register of pru
    • made the circuit design using Fritzing

Date : 1 July 2019

  • Till Now
    • testing the shift register 74hc299 with beagle bone black with the pre defined set of inputs
  • Blocker
    • the problem came out be the proper sync of the clock pulse

Date : 2 July 2019

  • Till Now
    • today i combined all the previously made assembly code into one and sync the clk that was the main problem that i faced while combining the code and the value for the different registers
    • made few videos in this whole process and the documentation work is pending that also get completed by tommorow
    • Today talked to @hendersa on the IRC

Date : 3 July 2019

Date : 4 July 2019

Date : 5 July 2019

  • Till Now
    • as was finding the solution to latch the data in the shift register buy some 4066 ic which is quad bilateral switch
    • it can help in controlled flow of data from the 74hc299 to input and output

Date : 5-7 July 2019

  • Till Now
    • I have to travel from Chandigarh to IIT Hyderabad which is around 1900 km from my native place
    • One thing that i miss and led to consequences as i forget to update my mentor about the Smart India Hackathon 2019 Hardware edition
    • our team got selected in one of the 250 team out of 20,000 total team from all across India.

Date : 8 July 2019

  • Till Now
    • I got a mail from @hendersa regarding enabling the latching feature of the 74hc299 by controlling the enable pin high and low
    • I started working on the suggestion provided by him regarding the necessary changes that are required to to get latched output in the file 74hc299_10_v1.p
  • Blocker
    • i am not able to devote my full time for some time at the project as i was little busy at the hackathon there at IIT Hyderabad

Date : 9 July 2019

  • Till Now
    • Tested the code with the logic analyser and started to get some high frequency signal in between it which corrupt the signal that i was sending to the shift register

Date : 10 July 2019

  • Till Now
    • i got the warning mail from the mentor today as i was i had made two mistake that were basically intolerable for any person (professionally speaking )
  1. i had not upload any progress on the wiki page ,github page etc. though i have the working file here on my local machine as i was testing the files for checking for their correctness
  2. and the foremost important mistake thing that i had done was not informing my mentor regarding our team selection in grand final in the Smart India Hackathon 2019 ( world largest hackathon organized by Govt. of India) in collaboration with other industries .That's give very unprofessional impact about me on them.