Difference between revisions of "CI20 Hardware"

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m (PMU: typo)
(HDMI: Added a note about the HDMI peripheral and its lack of documentation.)
 
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== Tech Spec overview ==
 
== Tech Spec overview ==
 +
 +
<imagemap>
 +
File:Ci20_V2_Top_Labelled.png|400px|right|View of the top of the Ci20 V2 board
 +
rect 29 4 96 98 [[#Ethernet|Ethernet RJ45]]
 +
rect 51 113 86 147 [[#Ethernet 2|Eth DM9000]]
 +
rect 107 8 138 60 [[#Button|Button]]
 +
rect 139 14 197 71 [[#HDMI|HDMI]]
 +
rect 175 85 198 138 [[#Dedicated UART header|UART 4]]
 +
rect 212 22 247 128 [[#EJTAG|EJTAG]]
 +
rect 259 21 292 78 [[#Audio|Audio In/Out]]
 +
rect 303 12 337 66 [[#Power|5V DC In]]
 +
rect 337 44 361 81 [[#Reset|Reset button]]
 +
rect 294 87 385 121 [[#USB A connector (right)|USB EHCI/OHCI]]
 +
rect 294 138 385 172 [[#USB A connector (left)|USB OTG Host]]
 +
rect 207 137 286 161 [[#Secondary expansion header|Expansion 2]]
 +
rect 296 180 323 195 [[#OTG VBUS jumper|USB OTG Select]]
 +
rect 323 180 365 195 [[#USB mini-OTG connector|USB OTG Device]]
 +
rect 98 134 118 168 [[#ActivityLEDs| Activity LEDs]]
 +
rect 216 313 323 388 [[#SDcard|SD Card]]
 +
rect 330 305 357 333 [[#LED|Power LED]]
 +
rect 173 349 203 388 [[#IR|IR]]
 +
rect 83 317 146 346 [[#Camera|Camera]]
 +
rect 48 177 100 212 [[#DDR/RAM|DDR]]
 +
rect 48 260 100 295 [[#DDR/RAM|DDR]]
 +
rect 130 198 198 266 [[#SoC|JZ4780]]
 +
rect 118 118 138 155 [[#Boot mode selector|Boot Sel]]
 +
rect 40 360 169 389 [[#Primary expansion header|Expansion 1]]
 +
</imagemap>
 +
<imagemap>
 +
File:Ci20_V2_Bottom_Labelled.png|400px|right|View of the bottom of the Ci20 V2 board
 +
rect 50 89 103 124 [[#DDR/RAM|DDR]]
 +
rect 50 174 103 209 [[#DDR/RAM|DDR]]
 +
rect 148 80 241 132 [[#ROM/NAND|NAND]]
 +
rect 269 174 310 211 [[#PMU|PMU]]
 +
rect 295 103 348 151 [[#WiFi/BT|BT/WiFi]]
 +
rect 354 119 386 155 [[#WiFi/BT|Antenna]]
 +
rect 157 200 198 235 [[#RTC|RTC]]
 +
rect 256 345 282 374 [[#Microphone switcher|Microphone Switcher]]
 +
</imagemap>
  
 
<imagemap>
 
<imagemap>
Line 15: Line 54:
 
rect 393 136 534 168 [[#USB A connector (right)|USB EHCI/OHCI]]
 
rect 393 136 534 168 [[#USB A connector (right)|USB EHCI/OHCI]]
 
rect 399 205 531 236 [[#USB A connector (left)|USB OTG Host]]
 
rect 399 205 531 236 [[#USB A connector (left)|USB OTG Host]]
rect 260 191 388 220 [[#Secondary 0.1" expansion header|Expansion 2]]
+
rect 260 191 388 220 [[#Secondary expansion header|Expansion 2]]
 
rect 388 246 441 275 [[#OTG VBUS jumper|USB OTG Select]]
 
rect 388 246 441 275 [[#OTG VBUS jumper|USB OTG Select]]
 
rect 442 249 507 280 [[#USB mini-OTG connector|USB OTG Device]]
 
rect 442 249 507 280 [[#USB mini-OTG connector|USB OTG Device]]
Line 42: Line 81:
 
{| class="wikitable"
 
{| class="wikitable"
 
! Feature
 
! Feature
! Details
+
! [[CI20 Hardware#Revision A|Rev A]]
 +
! [[CI20 Hardware#Revision B|Rev B]]
 +
! [[CI20 Hardware#Revision V2 .28current production.29|V2]]
 
|-
 
|-
 
| SoC
 
| SoC
| [[Ingenic JZ4780]]
+
| colspan=3 | [[Ingenic JZ4780]]
 
|-
 
|-
 
| CPU
 
| CPU
| Dual 1.2GHz [[XBurst]] MIPS32 little endian
+
| colspan=3 | Dual 1.2GHz [[XBurst]] MIPS32 little endian
 
|-
 
|-
 
| Caches
 
| Caches
| 32kI + 32kD per core, 512K shared L2
+
| colspan=3 | 32kI + 32kD per core, 512K shared L2
 
|-
 
|-
 
| RAM
 
| RAM
| 1Gbyte DDR3
+
| colspan=3 | 1Gbyte DDR3
 
|-
 
|-
 
| NAND
 
| NAND
| 8Gbytes NOR
+
| colspan=3 | 8 Gbyte
 
|-
 
|-
 
| SDcard
 
| SDcard
| 1x full size slot + 1x slot via expansion
+
| colspan=3 | 1x [[#SDcard|full size slot]] + 1x [[#Secondary expansion header|slot via secondary expansion header]]
 
|-
 
|-
 
| USB
 
| USB
| 1xUSB otg + 1xUSB host
+
| colspan=3 | 1x [[#USB A connector (left)|USB otg]] + 1x [[#USB A connector (right)|USB host]]
 
|-
 
|-
 
| Ethernet
 
| Ethernet
| 1x 10/200
+
| colspan=3 | 1x 10/100Mbps using [http://www.davicom.com.tw/userfile/24247/DM9000C-DS-P02-011808.pdf Davicom DM9000C controller] over 8-bit interface
 
|-
 
|-
 
| Wifi
 
| Wifi
| IW8103 wifi-? + BT4, built in ceramic aerial
+
| colspan=3 | [[#WiFi/BT|IW8103 wifi-? + BT4]], built in ceramic aerial
 
|-
 
|-
 
| GPU
 
| GPU
| SGX540
+
| colspan=3 | PowerVR SGX540
 
|-
 
|-
 
| Video
 
| Video
| Hardware video decode upto 1080p60
+
| colspan=3 | Hardware video decoder up to 1080p60
 
|-
 
|-
 
| Display
 
| Display
| HDMI, upto 2k resolution
+
| colspan=3 | [[#HDMI|HDMI]], up to 2k resolution
 
|-
 
|-
 
| Camera
 
| Camera
| ITU645 dedicated connector
+
| colspan=3 | ITU645 [[#Camera|dedicated connector]]
 
|-
 
|-
 
| GPIO
 
| GPIO
| 23 available on headers
+
| colspan=3 | 25 available on headers
 
|-
 
|-
 
| SPI
 
| SPI
| 2 ports on headers, with 4 chip selects
+
| colspan=3 | 2 ports on [[#Primary expansion header|primary]] & [[#Secondary expansion header|secondary expansion header]], with 4 chip selects
 
|-
 
|-
 
| I2C
 
| I2C
| One port on header
+
| colspan=3 | One port on [[#Primary expansion header|primary expansion header]]. Note: i2cdetect incorrectly shows some I2C addresses as full. Despite this, the I2C block works fine.
 
|-
 
|-
 
| ADC
 
| ADC
| 7 inputs on header, including 5-wire touch and battery monitoring functions
+
| colspan=3 | 7 inputs on [[#Secondary expansion header|secondary expansion header]], including 5-wire touch and battery monitoring functions
 
|-
 
|-
 
| UART
 
| UART
| 1 on dedicated header, 2 via pin headers
+
| colspan=3 | 1 on [[#Dedicated UART header|dedicated UART header]], 2 via [[#Primary expansion header|primary expansion header]]
 
|-
 
|-
 
| Audio
 
| Audio
| Audio in and out via 3.5mm 4-wire connector
+
| colspan=3 | Audio in and out via [[#Audio|3.5mm 4-wire connector]]
 
|-
 
|-
 
| JTAG
 
| JTAG
| Standard 14-pin MIPS EJTAG header
+
| colspan=3 | Standard [[#EJTAG|14-pin MIPS EJTAG header]]
 
|-
 
|-
 
| Transport Stream Interface
 
| Transport Stream Interface
| Via pin header
+
| colspan=3 | Via [[#Secondary expansion header|secondary expansion header]]
 
|-
 
|-
 
| Power
 
| Power
| 5V via 4mm (shield) x 1.7mm (pin) center positive connector
+
| colspan=3 | 5V via [[#Power|4mm (shield) x 1.7mm (pin) center positive connector]]
 
|-
 
|-
 
| Size
 
| Size
| Apprx 90x95mm
+
| colspan=3 | Approx 90x95mm
 +
|-
 +
| Activity LEDs
 +
| colspan=2 | || [[#ActivityLEDs|4 Activity LEDs]]
 +
|-
 +
| Reset Button
 +
| colspan=2 | || [[#Reset|Reset Button]]
 
|}
 
|}
 
== Files ==
 
The following links provide information (predominantly PDF files) about the SoC, board and components for the MIPS Creator CI20.
 
 
=== SoC Information ===
 
 
Overview on the Imagination [http://blog.imgtec.com/powervr/the-brand-new-ingenic-jz4780-soc-with-powervr-series5-graphics-makes-an-appearance-at-ces-2013 web site]
 
 
English page on the Ingenic [http://www.ingenic.cn/en/en/proinfo.php?id=15&pid=782&fid=782 web site]
 
 
FTP download from the Ingenic [ftp://ftp.ingenic.cn/SOC/JZ4780/JZ4780_DS.PDF ftp site]
 
 
[[JZ4780]] pdf datasheet from the [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/soc/JZ4780_ds.pdf CI20 file archive]
 
 
=== Programmers Manual ===
 
[[JZ4780]] pdf datasheet from the [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/soc/JZ4780_PM.pdf CI20 file archive]
 
 
=== Schematic ===
 
Schematic pdf from the [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/board/CI20_V1.0_schematic.PDF CI20 file archive]
 
 
=== Board components and identification ===
 
 
Board/component (BOM) identication pdf from the [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/board/CI20_V1.0_layout_with%20part%20number.pdf CI20 file archive]
 
 
DDR chip manual [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/peripherals/DDR/Consumer_DDR3_H5TQ2G8(6)3DFR(Rev1.0).pdf CI20 file archive]
 
 
Ethernet chip manual [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/peripherals/ethernet/DM9000-DS-F03-041906_1.pdf CI20 file archive]
 
 
NAND chip manual [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/peripherals/NAND/8055.K9GBG08UXA_1.0.pdf CI20 file archive]
 
 
Power Management Unit (PMU) chip manual [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/peripherals/PMU/ACT8600_Datasheet.pdf CI20 file archive]
 
 
Real Time Clock (RTC) chip manual [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/peripherals/RTC/PT7C4337.pdf CI20 file archive]
 
 
=== Expander pinouts ===
 
Main expander pinout and function diagram pdf from the [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/board/CI20_V1.0_expander_pinout.pdf CI20 file archive]
 
 
Secondary expander pinout and function diagram pdf from the [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/board/CI20_V1.0_expander2_pinout.pdf CI20 file archive]
 
 
Dedicated UART header pinout and function diagram pdf from the [http://d2w7gz3tvxr77c.cloudfront.net/CI20/hardware/board/CI20_V1.0_uart_pinout.pdf CI20 file archive]
 
 
== Source code ==
 
The source code is hosted on github, and in the process of being upstreamed.
 
 
Please see the [[CI20 Dev Zone#Source Code|Dev Zone]] page for details.
 
 
== SDcard images ==
 
Please see the [[CI20_Downloads|Downloads]] page for links to the SDcard images.
 
  
 
== Connectors ==
 
== Connectors ==
=== Overview ===
 
Starting with the power connector, going anti-clockwise (ish) as you face the front of the board:
 
  
 
{| class="wikitable"
 
{| class="wikitable"
Line 175: Line 172:
 
| 4mm shield x 1.7mm pin 5V centre positive
 
| 4mm shield x 1.7mm pin 5V centre positive
 
|-
 
|-
| [[#Audio|Audio]]
+
| [[#HDMI|HDMI]]
| J9
+
| J3
| 3.5mm 4-pin (stereo out + mic in), with auto-sense chip to handle both OMTP and CTIA headsets
+
| Full size HDMI out, including audio support
 
|-
 
|-
| [[#EJTAG|EJTAG]]
+
| [[#USB A connector (left)|USB A connector (left)]]
| J58
+
| J24
| Standard MIPS 14pin EJTAG connector
+
| Paralleled with the mini OTG connector (note, they are not separate ports - do not plug into both at once!)
 
|-
 
|-
| [[#Secondary 0.1" expansion header|Secondary 0.1" expansion header]]
+
| [[#USB A connector (right)|USB A connector (right)]]
| J5
+
| J23
| Carries 5v and 3.3v power out, transport stream, ADC, GPIO, SynchronousSerial(SPI) and MSC(SDcard) functions
+
| From the EHCI host controller block
 
|-
 
|-
| [[#HDMI|HDMI]]
+
| [[#USB mini-OTG connector|USB mini-OTG connector]]
| J3
+
| J8
| Full size HDMI out, including audio support
+
| Paralleled with the full size A connector next to it.
 
|-
 
|-
| [[#Button|Button]]
+
| [[#OTG VBUS jumper|OTG VBUS jumper]]
| SW1
+
| JP2
| Boot time selector (see boot selector table). Can also be read from software, and create GPIO interrupt/ Note, this is <b>not</b> a reset button!
+
| Selects VBUS enabling on OTG port to enable master or slave functionality
 
|-
 
|-
 
| [[#Ethernet|Ethernet]]
 
| [[#Ethernet|Ethernet]]
 
| J11
 
| J11
 
| Standard RJ45 connector, with built in link and activity lights
 
| Standard RJ45 connector, with built in link and activity lights
 +
|-
 +
| [[#Audio|Audio]]
 +
| J9
 +
| 3.5mm 4-pin (stereo out + mic in), with auto-sense chip to handle both OMTP and CTIA headsets
 +
|-
 +
| [[#Button|Button]]
 +
| SW1
 +
| Boot time selector (see [[#Boot mode selector|boot selector table]]). Can also be read from software as GPIO. Note, this is <b>not</b> a reset button!
 +
|-
 +
| [[#Reset|Reset Button (V2 only)]]
 +
| RESET
 +
| System Reset button
 
|-
 
|-
 
| [[#Boot mode selector|Boot mode selector]]
 
| [[#Boot mode selector|Boot mode selector]]
Line 203: Line 212:
 
| Used to choose auto-boot from NAND or SDcard slot, predominantly.
 
| Used to choose auto-boot from NAND or SDcard slot, predominantly.
 
|-
 
|-
| [[#Primary expansion header|Primary expansion connector]]
+
| [[#SDcard|SDcard]]
| JP4
+
| J13
| 26-pin (2x13) 'RPi compatible' 0.1" pitch expansion connector, carrying power, UART, SynchronousSerial, I2C and GPIO functions.
+
| Full size SDcard slot, can be used for storage and/or direct boot
 
|-
 
|-
 
| [[#Camera|Camera]]
 
| [[#Camera|Camera]]
Line 219: Line 228:
 
| bi-colour status LED (red/blue), wired to USB power enable line
 
| bi-colour status LED (red/blue), wired to USB power enable line
 
|-
 
|-
| [[#SDcard|SDcard]]
+
| [[#ActivityLEDs|4 Activity LEDs (V2 only)]]
| J13
+
| LED0/1/2/3
| Full size SDcard slot, can be used for storage and/or direct boot
+
| Red activity LEDs available via /sys/class/leds/
 
|-
 
|-
| [[#USB mini-OTG connector|USB mini-OTG connector]]
+
| [[#Dedicated UART header|UART]]
| J8
+
| J57
| Paralleled with the full size A connector next to it.
+
| Dedicated 4-pin UART header
 
|-
 
|-
| [[#OTG VBUS jumper|OTG VBUS jumper]]
+
| [[#Primary expansion header|Primary expansion connector]]
| JP2
+
| JP4
| Selects VBUS enabling on OTG port to enable master or slave functionality
+
| 26-pin (2x13) 'RPi compatible' 0.1" pitch expansion connector, carrying power, UART, SynchronousSerial, I2C and GPIO functions.
 
|-
 
|-
| [[#USB A connector (left)|USB A connector (left)]]
+
| [[#Secondary expansion header|Secondary expansion header]]
| J24
+
| J5
| Paralleled with the mini OTG connector (note, they are not separate ports - do not plug into both at once!)
+
| Carries 5v and 3.3v power out, transport stream, ADC, GPIO, SynchronousSerial(SPI) and MSC(SDcard) functions
 
|-
 
|-
| [[#USB A connector (right)|USB A connector (right)]]
+
| [[#EJTAG|EJTAG]]
| J23
+
| J58
| From the EHCI host controller block
+
| Standard MIPS 14pin EJTAG connector
|-
 
| [[#Dedicated UART header|UART]]
 
| J57
 
| Dedicated 4-pin UART header
 
 
|}
 
|}
  
==== Power ====
+
=== Power ===
The power connector is a 5V 4mm (shield) x 1.7mm (pin) center positive connector. It takes 5V only.
+
The power connector is a 5V 4mm (shield) x 1.7mm (pin) center positive connector. It takes 5V only. Note that this connection is identical to that of the original Sony PSP, so power cables intended for that console also work for the CI20.
  
When somebody measures the current draw - maybe add it here?
+
{| class="wikitable"
 +
! State
 +
! Current draw @ 5V
 +
|-
 +
| Power off
 +
| 0 mA
 +
|-
 +
| Suspended
 +
| 30 mA
 +
|-
 +
| Idle (no devices plugged in, Wi-Fi off)
 +
| 210 mA
 +
|-
 +
| Maximum usage (Ethernet, Wi-Fi, SDcard, CPU, GPU all stressed)
 +
| 750 - 800 mA
 +
|}
  
==== Audio ====
+
{| class="wikitable"
Standard 4-pin headset connector, with auto OMTP/CTIA detection (so should work with any standard 4-pin headset).
+
! Device
 
+
! Current draw @ 5V
==== EJTAG ====
 
14-pin MIPS EJTAG headers. See projects for proposed OpenOCD/wiggler support project.
 
 
 
==== Secondary 0.1" expansion header ====
 
Pinout diagram for the secondary CI20 0.1" pitch 16 pin header
 
{| style="border-collapse:collapse"
 
|-
 
! style="width:100px" | 3nd func
 
! style="width:100px" | 2nd func
 
! style="width:100px" | GPIO
 
! style="width:100px" | schematic
 
! style="width:100px" | pin
 
! style="width:100px" | pin
 
! style="width:100px" | schematic
 
! style="width:100px" | GPIO
 
! style="width:100px" | 2nd func
 
! style="width:100px" | 3rd func
 
 
|-
 
|-
|colspan=3|
+
| HDMI
|style="background-color: #C7C7C7; text-align:right"| +3v3
+
| trace
!style="border-left: solid; border-top: solid"| 1
 
!style="border-right: solid; border-top: solid"| 2
 
|style="background-color: #C7C7C7"| 5V_IN
 
 
|-
 
|-
|style="background-color: #C3BD97; text-align:right"| TSFRM
+
| Wi-Fi - in use
|style="background-color: #8DB4E2; text-align:right"| MSC2_D3
+
| 100 mA
|style="background-color: #FCD4B4; text-align:right"| PB31
 
|style="background-color: #E6B8B7; text-align:right"| SSI1_CE0
 
!style="border-left: solid"| 3
 
!style="border-right: solid"| 4
 
|style="background-color: #E6B8B7"| SSI1_CLK
 
|style="background-color: #FCD4B4"| PB28
 
|style="background-color: #8DB4E2"| MSC2_CLK
 
|style="background-color: #C3BD97"| TSCLK
 
 
|-
 
|-
|style="background-color: #C3BD97; text-align:right"| TSSTR
+
| Wi-Fi - idle
|style="background-color: #8DB4E2; text-align:right"| MSC2_CMI
+
| trace with spikes of around 40 mA
|style="background-color: #FCD4B4; text-align:right"| PB29
 
|style="background-color: #E6B8B7; text-align:right"| SSI1_DT
 
!style="border-left: solid"| 5
 
!style="border-right: solid"| 6
 
|style="background-color: #E6B8B7"| SSI1_DR
 
|style="background-color: #FCD4B4"| PB20
 
|style="background-color: #8DB4E2"| MSC2_D0
 
|style="background-color: #C3BD97"| TSDIO
 
 
|-
 
|-
|style="background-color: #C3BD97; text-align:right"| TSDI1
+
| Ethernet - in use
|style="background-color: #8DB4E2; text-align:right"| MSC2_D1
+
| 150 mA
|style="background-color: #FCD4B4; text-align:right"| PB21
 
|style="background-color: #E6B8B7; text-align:right"| SSI1_CE1
 
!style="border-left: solid"| 7
 
!style="border-right: solid"| 8
 
|style="background-color: #E6B8B7"| SSI1_GPC
 
|style="background-color: #FCD4B4"| PB30
 
|style="background-color: #8DB4E2"| MSC2_D2
 
|style="background-color: #C3BD97"| TSFAIL
 
 
|-
 
|-
|colspan=3 rowspan=4|
+
| Ethernet - idle
|style="background-color: #D7E3BC; text-align:right"| XP
+
| 120 mA
!style="border-left: solid"| 9
 
!style="border-right: solid"| 10
 
|style="background-color: #D7E3BC"| XN
 
 
|-
 
|-
|style="background-color: #D7E3BC; text-align:right"| YP
+
| CPU + Memory - in use (compared to idle)
!style="border-left: solid"| 11
+
| 90 mA
!style="border-right: solid"| 12
 
|style="background-color: #D7E3BC"| YN
 
 
|-
 
|-
|style="background-color: #D7E3BC; text-align:right"| AUX1
+
| SDCard - writing
!style="border-left: solid"| 13
+
| 90 mA
!style="border-right: solid"| 14
 
|style="background-color: #D7E3BC"| AUX2
 
 
|-
 
|-
|style="background-color: #D7E3BC; text-align:right"| VBAT
+
| SDCard - reading
!style="border-left: solid; border-bottom: solid"| 15
+
| 60 mA
!style="border-right: solid; border-bottom: solid"| 16
 
|style="background-color: #C7C7C7"| GND
 
 
|}
 
|}
  
 +
=== HDMI ===
 +
Full sized HDMI connection with audio out support as well. The HDMI block on the JZ4780 supports HDMI v1.4a, and appears to be a Synopsys DesignWare HDMI controller, although this is not documented in the JZ4780 programming manual.
 +
 +
In the 3.18 kernel the code is found at drivers/gpu/drm/jz4780, but seems to live in a more generic form at drivers/gpu/drm/bridge/synopsys/dw-hdmi.c [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c in the mainline kernel].
 +
 +
=== USB A connector (left) ===
 +
Paralleled with the mini-OTG connector.
 +
 +
=== USB A connector (right) ===
 +
Connected to the EHCI USB controller in the SoC.
 +
 +
=== USB mini-OTG connector ===
 +
Is paralleled with the left hand USB A connector - do <b>not</b> plug into both of these at once.  Has the OTG VBUS controlled by the jumper next to it.
 +
 +
=== OTG VBUS jumper ===
 +
Controls the VBUS for the OTG ports-
  
{| style="border-collapse:collapse"
+
Jumper shorted = HOST mode.
!style="width:100px" | Key
+
 
|style="width:100px; background-color: #C7C7C7" | Power
+
Jumper not shorted = Device mode.
|style="width:100px; background-color: #C3BD97" | TSSI
+
 
|style="width:100px; background-color: #D7E3BC" | ADC
+
=== Ethernet ===
|style="width:100px; background-color: #FCD4B4" | GPIO
+
10/100 RJ45, connects to the DM9000 chipset.
|style="width:100px; background-color: #E6B8B7" | SSI
+
 
|style="width:100px; background-color: #8DB4E2" | MSC
+
=== Audio ===
 +
Standard 4-pin headset connector, with auto OMTP/CTIA detection (so should work with any standard 4-pin headset).
 +
 
 +
=== Button ===
 +
The button between HDMI and Ethernet is not a reset button - it is boot_select0. Combining this button with JP3, it is possible to boot the Ci20 from USB or MSC0.
 +
 
 +
Once the kernel has been loaded, the button can be used as a GPIO - it is pin {{CI20 GPIO|PD|17}}.
 +
 
 +
In the 3.15 kernel, the GPIO is number 113. You can export the GPIO via
 +
 
 +
echo 113 > /sys/class/gpio/export
 +
 
 +
=== Boot mode selector ===
 +
See the silkscreen on the board and the section at the end of the [[CI20 Hardware#Programmers Manual|JZ4780 programmers manual]].
 +
Fundamentally you can boot from the on-board NAND or direct off the SDcard without having to press the button during boot. There is also a USB boot function available, but it is not a standard DFU type boot, and requires JZ4780 specific host support.
 +
 
 +
{| class="wikitable"
 +
|-
 +
! BOOT_SEL[2:1:0] !! JP3 Jumper (BOOT_SEL1, {{CI20 GPIO|PD|18}}) !! [[#Button|SW1 Button]] (BOOT_SEL0, {{CI20 GPIO|PD|17}}) !! Boot Mode
 +
|-
 +
| 110 || Pins 1 & 2 shorted || Not pressed || [[#ROM/NAND|NAND flash]] at CS1
 +
|-
 +
| 100 || Pins 2 & 3 shorted || Not pressed || [[#SDcard|SD Card]] at MSC1
 +
|-
 +
| 111 || Pins 1 & 2 shorted || Pressed || USB device
 
|-
 
|-
! Version
+
| 101 || Pins 2 & 3 shorted || Pressed || SD NAND flash at MSC0
| 1.2
 
 
|}
 
|}
  
==== HDMI ====
+
=== SDcard ===
Full sized HDMI connection with audio out support as well. Can somebody confirm the HDMI version support (1.2a?), and also the number of audio out channels? (2, 5.1 ???).
+
Standard pinout full sized SD/MMC slot that can be used for direct booting, or for bulk storage (standard MTD support under Linux). It is wired to the MSC0 block in the SoC.
 +
 
 +
=== Camera ===
 +
[[File:CI20_camera_small.JPG|200px|thumb|right|Closeup of compatible camera]]
 +
[[File:Ci20_camera_back.jpg|200px|thumb|right|Closeup of back of compatible camera]]
 +
[[File:CI20_camera_fitted_small.JPG|200px|thumb|left|Camera unit fitted]]
 +
The camera connector is 24 pin (26 pins on the schematic - two of which are the side ground solder tabs on the connector itself - the actual cable interface is 24 pin), and CMOS DVP 8-bit camera compatible.  
  
==== Button ====
+
The Omnivision OV5640 5Mpixel unit can be used with the CI20 (often labelled FD5640 on the actual part)
The button between HDMI and Ethernet is not a reset button.
 
  
It is boot_select0. Combined with JP3, it can be used to boot the CI20 from the USB.
+
The connector installed on the CI20 is 24-PIN 0.5Pitch Bottom Contact FPC Connector
  
It can also be used as a gpio once the CI20 is powered up. The boot_sel0 pin is connected to PD17.
+
A camera module reported to be working by a community member [https://groups.google.com/forum/#!topic/mips-creator-ci20/Vv6nZBsiv-4 here]
  
Pinmux options can be checked to see which gpio is PD17 in kernel you booted.
+
'''Note''' Be aware that there are some SMT components directly under where the camera unit sits. If your camera unit has a conductive rear surface then this may short out on the board. Symptoms we have seen include board resets. Please insulate the area either on the PCB or the back of the camera unit to avoid this.
 +
<br clear=all>
  
In the 3.15 kernel, the gpio is number 113.  
+
=== IR ===
 +
The CI20 has an infrared remote control receiver (part IRM-2638A, carrier frequency 37.9kHz), which is connected to GPIO {{CI20 GPIO|PE|3}} for software decoding.
  
You can export the gpio via
+
=== LED ===
 +
The CI20 board features a dual colour red & blue LED. It is controlled by GPIO {{CI20 GPIO|PF|15}}, which also controls the USB VBUS supply. When {{CI20 GPIO|PF|15}} is high the LED lights red, when {{CI20 GPIO|PF|15}} is low it lights blue. Software cannot power off the LED. A simple way to toggle the LED colour is to write to the PFPAT0S & PFPAT0C registers from the U-boot shell, in order to toggle the {{CI20 GPIO|PF|15}} GPIO. The following example will toggle the colours rapidly, leading to the LED appearing purple:
  
  echo 113 > /sys/class/gpio/export
+
  <nowiki>while true; do mw.l 0xb0010548 0x8000; mw.l 0xb0010544 0x8000; done</nowiki>
  
And then use it.
+
=== ActivityLEDs ===
 +
Version 2 of the Ci20 board adds 4 red activity LEDs. These LEDs are exposed via sysfs as described [[CI20_GPIO_LED_Blink_Tutorial#Example_2:_Using_the_onboard_LEDs_of_Ci20_V2_boards | here]].
  
==== Ethernet ====
+
=== Reset ===
10/100 RJ45, connects to the DM9000 chipset.
+
Version 2 of the Ci20 board adds a system reset button.
  
==== Boot mode selector ====
+
=== Dedicated UART header ===
See the silkscreen on the board and the section at the end of the JZ4780 programmers manual.
+
Pinout and other functions of the dedicated UART header. This is uart4 of the SoC. Note that uart0 is on the [[#Primary expansion header|26pin main expansion header]].
Fundamentally you can boot from the on-board NAND or direct off the SDcard without having to press the button during boot. There is also a USB boot function available, but it is not a standard DFU type boot, and requires JZ4780 specific host support.
 
  
{| class="wikitable"
+
{| style="border-collapse:collapse"
 
|-
 
|-
! Boot Source !! BOOT_SEL (JP3) Jumper !! Button
+
! style="width:100px" | pin
 +
! style="width:100px" | schematic
 +
! style="width:100px" | GPIO
 +
! style="width:100px" | 2nd func
 +
! style="width:100px" | 3rd func
 
|-
 
|-
| NAND || Pins 1 & 2 shorted || Not pressed
+
!style="border-left: solid; border-right: solid; border-top: solid"| 1
 +
|style="background-color: #C7C7C7"| +3v3
 
|-
 
|-
| SD Card || Pins 2 & 3 shorted || Not pressed
+
!style="border-left: solid; border-right: solid"| 2
 +
|style="background-color: #E6B8B7"| TXD
 +
|style="background-color: #FCD4B4"| {{CI20 GPIO|PC|10}}
 +
|style="background-color: #8DB4E2"| LCD_SPL
 +
|style="background-color: #8DB4E2"| LCD_G0
 
|-
 
|-
| USB || Pins 1 & 2 shorted || Pressed
+
!style="border-left: solid; border-right: solid"| 3
 +
|style="background-color: #C7C7C7"| GND
 
|-
 
|-
| MSC0 || Pins 2 & 3 shorted || Pressed
+
!style="border-left: solid; border-right: solid; border-bottom: solid"| 4
 +
|style="background-color: #E6B8B7"| RXD
 +
|style="background-color: #FCD4B4"| {{CI20 GPIO|PC|20}}
 +
|style="background-color: #8DB4E2"| LCD_CLS
 +
|style="background-color: #8DB4E2"| LCD_R0
 
|}
 
|}
  
==== Primary expansion header ====
+
 
 +
{| style="border-collapse:collapse"
 +
!style="width:100px" | Key
 +
|style="width:100px; background-color: #C7C7C7" | Power
 +
|style="width:100px; background-color: #E6B8B7" | UART4
 +
|style="width:100px; background-color: #FCD4B4" | GPIO
 +
|style="width:100px; background-color: #8DB4E2" | LCD
 +
|}
 +
 
 +
=== Primary expansion header ===
 
Pinout diagram for the main CI20 0.1" pitch 26 pin header
 
Pinout diagram for the main CI20 0.1" pitch 26 pin header
 
{| style="border-collapse:collapse"
 
{| style="border-collapse:collapse"
Line 407: Line 444:
 
|-
 
|-
 
|
 
|
|style="background-color: #FCD4B4; text-align:right"| PD30
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PD|30}}
 
|style="background-color: #8DB4E2; text-align:right"| I2C1_SDA
 
|style="background-color: #8DB4E2; text-align:right"| I2C1_SDA
 
!style="border-left: solid"| 3
 
!style="border-left: solid"| 3
Line 414: Line 451:
 
|-
 
|-
 
|
 
|
|style="background-color: #FCD4B4; text-align:right"| PD31
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PD|31}}
 
|style="background-color: #8DB4E2; text-align:right"| I2C1_SCK
 
|style="background-color: #8DB4E2; text-align:right"| I2C1_SCK
 
!style="border-left: solid"| 5
 
!style="border-left: solid"| 5
Line 421: Line 458:
 
|-
 
|-
 
|style="background-color: #D7E3BC; text-align:right"| UART1_TXD
 
|style="background-color: #D7E3BC; text-align:right"| UART1_TXD
|style="background-color: #FCD4B4; text-align:right"| PD28
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PD|28}}
 
|style="background-color: #FCD4B4; text-align:right"| GPIO1
 
|style="background-color: #FCD4B4; text-align:right"| GPIO1
 
!style="border-left: solid"| 7
 
!style="border-left: solid"| 7
 
!style="border-right: solid"| 8
 
!style="border-right: solid"| 8
 
|style="background-color: #ECF1DD"| UART0_TXD
 
|style="background-color: #ECF1DD"| UART0_TXD
|style="background-color: #FCD4B4"| PF3
+
|style="background-color: #FCD4B4"| {{CI20 GPIO|PF|3}}
 
|-
 
|-
 
|colspan="2"|
 
|colspan="2"|
Line 433: Line 470:
 
!style="border-right: solid"| 10
 
!style="border-right: solid"| 10
 
|style="background-color: #ECF1DD"| UART0_RXD
 
|style="background-color: #ECF1DD"| UART0_RXD
|style="background-color: #FCD4B4"| PF0
+
|style="background-color: #FCD4B4"| {{CI20 GPIO|PF|0}}
 
|style="background-color: #CBC0D8"| <strike>GPS_CLK</strike>
 
|style="background-color: #CBC0D8"| <strike>GPS_CLK</strike>
 
|-
 
|-
 
|style="background-color: #D7E3BC; text-align:right"| UART1_RXD
 
|style="background-color: #D7E3BC; text-align:right"| UART1_RXD
|style="background-color: #FCD4B4; text-align:right"| PD26
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PD|26}}
 
|style="background-color: #FCD4B4; text-align:right"| GPIO2
 
|style="background-color: #FCD4B4; text-align:right"| GPIO2
 
!style="border-left: solid"| 11
 
!style="border-left: solid"| 11
 
!style="border-right: solid"| 12
 
!style="border-right: solid"| 12
 
|style="background-color: #C4BD96"| <strike>PWM</strike>
 
|style="background-color: #C4BD96"| <strike>PWM</strike>
|style="background-color: #FCD4B4"| PF5
+
|style="background-color: #FCD4B4"| {{CI20 GPIO|PE|5}}
 
|style="background-color: #C4BD96"| <strike>PWM5</strike>
 
|style="background-color: #C4BD96"| <strike>PWM5</strike>
|style="background-color: #C3D79A"| UART3_TXD
+
|style="background-color: #C3D69B"| UART3_TXD
 
|style="background-color: #D99593"| <strike>SCLK_RSTN</strike>
 
|style="background-color: #D99593"| <strike>SCLK_RSTN</strike>
 
|-
 
|-
 
|style="background-color: #D7E3BC; text-align:right"| UART1_CTS
 
|style="background-color: #D7E3BC; text-align:right"| UART1_CTS
|style="background-color: #FCD4B4; text-align:right"| PD27
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PD|27}}
 
|style="background-color: #FCD4B4; text-align:right"| GPIO3
 
|style="background-color: #FCD4B4; text-align:right"| GPIO3
 
!style="border-left: solid"| 13
 
!style="border-left: solid"| 13
Line 455: Line 492:
 
|-
 
|-
 
|style="background-color: #D7E3BC; text-align:right"| UART1_RTS
 
|style="background-color: #D7E3BC; text-align:right"| UART1_RTS
|style="background-color: #FCD4B4; text-align:right"| PD29
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PD|29}}
 
|style="background-color: #FCD4B4; text-align:right"| GPIO4
 
|style="background-color: #FCD4B4; text-align:right"| GPIO4
 
!style="border-left: solid"| 15
 
!style="border-left: solid"| 15
 
!style="border-right: solid"| 16
 
!style="border-right: solid"| 16
 
|style="background-color: #FCD4B4"| GPIO5
 
|style="background-color: #FCD4B4"| GPIO5
|style="background-color: #FCD4B4"| PF1
+
|style="background-color: #FCD4B4"| {{CI20 GPIO|PF|1}}
 
|style="background-color: #ECF1DD"| UART0_CTS
 
|style="background-color: #ECF1DD"| UART0_CTS
 
|style="background-color: #CBC0D8"| <strike>GPS_MAG</strike>
 
|style="background-color: #CBC0D8"| <strike>GPS_MAG</strike>
Line 469: Line 506:
 
!style="border-right: solid"| 18
 
!style="border-right: solid"| 18
 
|style="background-color: #FCD4B4"| GPIO6
 
|style="background-color: #FCD4B4"| GPIO6
|style="background-color: #FCD4B4"| PF2
+
|style="background-color: #FCD4B4"| {{CI20 GPIO|PF|2}}
 
|style="background-color: #ECF1DD"| UART0_RTS
 
|style="background-color: #ECF1DD"| UART0_RTS
 
|style="background-color: #CBC0D8"| <strike>GPS_SIG</strike>
 
|style="background-color: #CBC0D8"| <strike>GPS_SIG</strike>
 
|-
 
|-
 
|style="background-color: #E5B6B5; text-align:right"| SSI1_DT
 
|style="background-color: #E5B6B5; text-align:right"| SSI1_DT
|style="background-color: #FCD4B4; text-align:right"| PE17
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PE|17}}
 
|style="background-color: #E5B6B5; text-align:right"| SSI0_DT
 
|style="background-color: #E5B6B5; text-align:right"| SSI0_DT
 
!style="border-left: solid"| 19
 
!style="border-left: solid"| 19
Line 481: Line 518:
 
|-
 
|-
 
|style="background-color: #E5B6B5; text-align:right"| SSI1_DR
 
|style="background-color: #E5B6B5; text-align:right"| SSI1_DR
|style="background-color: #FCD4B4; text-align:right"| PE14
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PE|14}}
 
|style="background-color: #E5B6B5; text-align:right"| SSI0_DR
 
|style="background-color: #E5B6B5; text-align:right"| SSI0_DR
 
!style="border-left: solid"| 21
 
!style="border-left: solid"| 21
 
!style="border-right: solid"| 22
 
!style="border-right: solid"| 22
 
|style="background-color: #FCD4B4"| GPIO7
 
|style="background-color: #FCD4B4"| GPIO7
|style="background-color: #FCD4B4"| PE8
+
|style="background-color: #FCD4B4"| {{CI20 GPIO|PE|8}}
|style="background-color: #C4D79B"| UART3_CTS
+
|style="background-color: #C3D69B"| UART3_CTS
 
|style="background-color: #D89592"| <strike>BCLK_AD</strike>
 
|style="background-color: #D89592"| <strike>BCLK_AD</strike>
 
|-
 
|-
 
|style="background-color: #E5B6B5; text-align:right"| SSI1_CLK
 
|style="background-color: #E5B6B5; text-align:right"| SSI1_CLK
|style="background-color: #FCD4B4; text-align:right"| PE15
+
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PE|15}}
 
|style="background-color: #E5B6B5; text-align:right"| SSI0_CLK
 
|style="background-color: #E5B6B5; text-align:right"| SSI0_CLK
 
!style="border-left: solid"| 23
 
!style="border-left: solid"| 23
 
!style="border-right: solid"| 24
 
!style="border-right: solid"| 24
 
|style="background-color: #E5B6B5"| SSI0_CE0
 
|style="background-color: #E5B6B5"| SSI0_CE0
|style="background-color: #FCD4B4"| PE16
+
|style="background-color: #FCD4B4"| {{CI20 GPIO|PE|16}}
 
|style="background-color: #E5B6B5"| SSI1_CE0
 
|style="background-color: #E5B6B5"| SSI1_CE0
 
|-
 
|-
Line 504: Line 541:
 
!style="border-right: solid; border-bottom: solid"| 26
 
!style="border-right: solid; border-bottom: solid"| 26
 
|style="background-color: #E5B6B5"| SSI0_CE1
 
|style="background-color: #E5B6B5"| SSI0_CE1
|style="background-color: #FCD4B4"| PE18
+
|style="background-color: #FCD4B4"| {{CI20 GPIO|PE|18}}
 
|style="background-color: #E5B6B5"| SSI1_CE1
 
|style="background-color: #E5B6B5"| SSI1_CE1
 
|}
 
|}
Line 514: Line 551:
 
|style="width:100px; background-color: #ECF1DD" | UART0
 
|style="width:100px; background-color: #ECF1DD" | UART0
 
|style="width:100px; background-color: #D7E3BC" | UART1
 
|style="width:100px; background-color: #D7E3BC" | UART1
|style="width:100px; background-color: #C4D79B" | UART3
+
|style="width:100px; background-color: #C3D69B" | UART3
 
|style="width:100px; background-color: #E5B6B5" | SSI
 
|style="width:100px; background-color: #E5B6B5" | SSI
 
|-
 
|-
 
|
 
|
|style="width:100px; background-color: #CBC0D8" | <strike>GPS</strike>
+
|style="width:100px; background-color: #CBC0D8" | <strike>GPS</strike><ref group="primary" name="gps" />
 
|style="width:100px; background-color: #8DB4E2" | I2C
 
|style="width:100px; background-color: #8DB4E2" | I2C
|style="width:100px; background-color: #D89592" | <strike>I2S</strike>
+
|style="width:100px; background-color: #D89592" | <strike>I2S</strike><ref group="primary" name="i2s" />
 
|style="width:100px; background-color: #FCD4B4" | GPIO
 
|style="width:100px; background-color: #FCD4B4" | GPIO
|style="width:100px; background-color: #C4BD96" | <strike>PWM</strike>
+
|style="width:100px; background-color: #C4BD96" | <strike>PWM</strike><ref group="primary" name="pwm" />
|-
 
! Version
 
| 1.5
 
 
|}
 
|}
  
# Note that the PWM facility is unavailable as this PWM unit is used by the Linux kernel SMP timer code
+
<references group="primary">
# Note that the GPS interface is unavailable as it is (believed to be) electrically incompliant
+
<ref name="pwm">Note that the PWM facility is unavailable as this PWM unit is used by the Linux kernel SMP timer code</ref>
# Note that the I2S block is not useable on the header as not all I2S pins are brought out
+
<ref name="gps">Note that the GPS interface is unavailable as it is (believed to be) electrically incompliant</ref>
 +
<ref name="i2s">Note that the I2S block is not useable on the header as not all I2S pins are brought out</ref>
 +
</references>
  
==== Camera ====
+
=== Secondary expansion header ===
[[File:CI20_camera_small.JPG|200px|thumb|right|Closeup of compatible camera]]
+
Pinout diagram for the secondary CI20 0.1" pitch 16 pin header
[[File:CI20_camera_fitted_small.JPG|200px|thumb|left|Camera unit fitted]]
+
{| style="border-collapse:collapse"
The camera connector is 24 pin (26 pins on the schematic - two of which are the side ground solder tabs on the connector itself - the actual cable interface is 24 pin), and CMOS DVP 8-bit camera compatible. The Omnivision OV5640 5Mpixel unit can be used with the CI20 (often labelled FD5640 on the actual part)
+
|-
<br clear=all>
+
! style="width:100px" | 3nd func
 +
! style="width:100px" | 2nd func
 +
! style="width:100px" | GPIO
 +
! style="width:100px" | schematic
 +
! style="width:100px" | pin
 +
! style="width:100px" | pin
 +
! style="width:100px" | schematic
 +
! style="width:100px" | GPIO
 +
! style="width:100px" | 2nd func
 +
! style="width:100px" | 3rd func
 +
|-
 +
|colspan=3|
 +
|style="background-color: #C7C7C7; text-align:right"| +3v3
 +
!style="border-left: solid; border-top: solid"| 1
 +
!style="border-right: solid; border-top: solid"| 2
 +
|style="background-color: #C7C7C7"| 5V_IN
 +
|-
 +
|style="background-color: #C3BD97; text-align:right"| TSFRM
 +
|style="background-color: #8DB4E2; text-align:right"| MSC2_D3
 +
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PB|31}}
 +
|style="background-color: #E6B8B7; text-align:right"| SSI1_CE0
 +
!style="border-left: solid"| 3
 +
!style="border-right: solid"| 4
 +
|style="background-color: #E6B8B7"| SSI1_CLK
 +
|style="background-color: #FCD4B4"| {{CI20 GPIO|PB|28}}
 +
|style="background-color: #8DB4E2"| MSC2_CLK
 +
|style="background-color: #C3BD97"| TSCLK
 +
|-
 +
|style="background-color: #C3BD97; text-align:right"| TSSTR
 +
|style="background-color: #8DB4E2; text-align:right"| MSC2_CMI
 +
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PB|29}}
 +
|style="background-color: #E6B8B7; text-align:right"| SSI1_DT
 +
!style="border-left: solid"| 5
 +
!style="border-right: solid"| 6
 +
|style="background-color: #E6B8B7"| SSI1_DR
 +
|style="background-color: #FCD4B4"| {{CI20 GPIO|PB|20}}
 +
|style="background-color: #8DB4E2"| MSC2_D0
 +
|style="background-color: #C3BD97"| TSDIO
 +
|-
 +
|style="background-color: #C3BD97; text-align:right"| TSDI1
 +
|style="background-color: #8DB4E2; text-align:right"| MSC2_D1
 +
|style="background-color: #FCD4B4; text-align:right"| {{CI20 GPIO|PB|21}}
 +
|style="background-color: #E6B8B7; text-align:right"| SSI1_CE1
 +
!style="border-left: solid"| 7
 +
!style="border-right: solid"| 8
 +
|style="background-color: #E6B8B7"| SSI1_GPC
 +
|style="background-color: #FCD4B4"| {{CI20 GPIO|PB|30}}
 +
|style="background-color: #8DB4E2"| MSC2_D2
 +
|style="background-color: #C3BD97"| TSFAIL
 +
|-
 +
|colspan=3 rowspan=4|
 +
|style="background-color: #D7E3BC; text-align:right"| XP
 +
!style="border-left: solid"| 9
 +
!style="border-right: solid"| 10
 +
|style="background-color: #D7E3BC"| XN
 +
|-
 +
|style="background-color: #D7E3BC; text-align:right"| YP
 +
!style="border-left: solid"| 11
 +
!style="border-right: solid"| 12
 +
|style="background-color: #D7E3BC"| YN
 +
|-
 +
|style="background-color: #D7E3BC; text-align:right"| AUX1
 +
!style="border-left: solid"| 13
 +
!style="border-right: solid"| 14
 +
|style="background-color: #D7E3BC"| AUX2
 +
|-
 +
|style="background-color: #D7E3BC; text-align:right"| VBAT
 +
!style="border-left: solid; border-bottom: solid"| 15
 +
!style="border-right: solid; border-bottom: solid"| 16
 +
|style="background-color: #C7C7C7"| GND
 +
|}
  
==== IR ====
 
Receive only. Anybody got details on the protocols supported by hardware, and if pure software can be used to support other protocols?
 
  
==== LED ====
+
{| style="border-collapse:collapse"
The CI20 board features a dual colour red & blue LED. It is controlled by GPIO PF15, which also controls the USB VBUS supply. When PF15 is high the LED lights red, when PF15 is low it lights blue. Software cannot power off the LED. A simple way to toggle the LED colour is to write to the PFPAT0S & PFPAT0C registers from the U-boot shell, in order to toggle the PF15 GPIO. The following example will toggle the colours rapidly, leading to the LED appearing purple:
+
!style="width:100px" | Key
 
+
|style="width:100px; background-color: #C7C7C7" | Power
<nowiki>while true; do mw.l 0xb0010548 0x8000; mw.l 0xb0010544 0x8000; done</nowiki>
+
|style="width:100px; background-color: #C3BD97" | TSSI
 
+
|style="width:100px; background-color: #D7E3BC" | ADC
==== SDcard ====
+
|style="width:100px; background-color: #FCD4B4" | GPIO
Standard pinout full sized SD/MMC slot. Can be used for direct booting, or for bulk storage (standard MTD support under Linux). Is wired to the MSC0 block in the SoC.
+
|style="width:100px; background-color: #E6B8B7" | SSI
 
+
|style="width:100px; background-color: #8DB4E2" | MSC
==== USB mini-OTG connector ====
+
|}
Is paralleled with the left hand USB A connector - do <b>not</b> plug into both of these at once.  Has the OTG VBUS controlled by the jumper next to it.
 
 
 
==== OTG VBUS jumper ====
 
Controls the VBUS for the OTG ports - would somebody like to describe the difference between having the connector fitted or not please.
 
 
 
==== USB A connector (left) ====
 
Paralleled with the mini-OTG connector.
 
  
==== USB A connector (right) ====
+
=== EJTAG ===
Connected to the EHCI USB controller in the SoC.
+
14-pin MIPS EJTAG headers. See proposed [[CI20 Projects#OpenOCD|OpenOCD/wiggler support project]].
 
 
==== Dedicated UART header ====
 
Pinout and other functions of the dedicated UART header. This is uart4 of the SoC. Note that uart0 is on the [[#Primary expansion header|26pin main expansion header]].
 
  
 
{| style="border-collapse:collapse"
 
{| style="border-collapse:collapse"
 
|-
 
|-
 +
! style="width:100px" | 3nd func
 +
! style="width:100px" | 2nd func
 +
! style="width:100px" | schematic
 +
! style="width:100px" | pin
 
! style="width:100px" | pin
 
! style="width:100px" | pin
 
! style="width:100px" | schematic
 
! style="width:100px" | schematic
! style="width:100px" | GPIO
 
! style="width:100px" | 2nd func
 
! style="width:100px" | 3rd func
 
 
|-
 
|-
!style="border-left: solid; border-right: solid; border-top: solid"| 1
+
|colspan=2|
|style="background-color: #C7C7C7"| +3v3
+
|style="background-color: #FAC090; text-align:right"| TRST_N
 +
!style="border-left: solid; border-top: solid"| 1
 +
!style="border-right: solid; border-top: solid"| 2
 +
|style="background-color: #C7C7C7"| GND
 +
|-
 +
|style="background-color: #95B3D7; text-align:right"| PS2_KCLK
 +
|style="background-color: #C3D69B; text-align:right"| UART3_RXD
 +
|style="background-color: #FAC090; text-align:right"| TDI_RXD
 +
!style="border-left: solid"| 3
 +
!style="border-right: solid"| 4
 +
|style="background-color: #C7C7C7"| GND
 +
|-
 +
|style="background-color: #95B3D7; text-align:right"| PS2_KDATA
 +
|style="background-color: #C3D69B; text-align:right"| UART3_TXD
 +
|style="background-color: #FAC090; text-align:right"| TDO_TXD
 +
!style="border-left: solid"| 5
 +
!style="border-right: solid"| 6
 +
|style="background-color: #C7C7C7"| GND
 
|-
 
|-
!style="border-left: solid; border-right: solid"| 2
+
|style="background-color: #95B3D7; text-align:right"| PS2_MDATA
|style="background-color: #E6B8B7"| TXD
+
|style="background-color: #C3D69B; text-align:right"| UART3_CTS
|style="background-color: #FCD4B4"| PC10
+
|style="background-color: #FAC090; text-align:right"| TMS
|style="background-color: #8DB4E2"| LCD_SPL
+
!style="border-left: solid"| 7
|style="background-color: #8DB4E2"| LCD_G0
+
!style="border-right: solid"| 8
 +
|style="background-color: #C7C7C7"| GND
 
|-
 
|-
!style="border-left: solid; border-right: solid"| 3
+
|style="background-color: #95B3D7; text-align:right"| PS2_MCLK
 +
|style="background-color: #C3D69B; text-align:right"| UART3_RTS
 +
|style="background-color: #FAC090; text-align:right"| TCK
 +
!style="border-left: solid"| 9
 +
!style="border-right: solid"| 10
 
|style="background-color: #C7C7C7"| GND
 
|style="background-color: #C7C7C7"| GND
 
|-
 
|-
!style="border-left: solid; border-right: solid; border-bottom: solid"| 4
+
|colspan=2|
|style="background-color: #E6B8B7"| RXD
+
|style="background-color: #FAC090; text-align:right"| RST_N
|style="background-color: #FCD4B4"| PC20
+
!style="border-left: solid"| 11
|style="background-color: #8DB4E2"| LCD_CLS
+
!style="border-right: solid"| 12
|style="background-color: #8DB4E2"| LCD_R0
+
| N/C
 +
|-
 +
|colspan=2|
 +
|style="text-align:right"| N/C
 +
!style="border-left: solid; border-bottom: solid"| 13
 +
!style="border-right: solid; border-bottom: solid"| 14
 +
|style="background-color: #C7C7C7"| 3V3
 
|}
 
|}
  
Line 594: Line 717:
 
{| style="border-collapse:collapse"
 
{| style="border-collapse:collapse"
 
!style="width:100px" | Key
 
!style="width:100px" | Key
|style="width:100px; background-color: #E6B8B7" | UART
 
|style="width:100px; background-color: #FCD4B4" | GPIO
 
|style="width:100px; background-color: #8DB4E2" | LCD
 
 
|style="width:100px; background-color: #C7C7C7" | Power
 
|style="width:100px; background-color: #C7C7C7" | Power
|-
+
|style="width:100px; background-color: #95B3D7" | PS2
! Version
+
|style="width:100px; background-color: #C3D69B" | UART3
| 1
+
|style="width:100px; background-color: #FAC090" | EJTAG<ref name="jtag" group="EJTAG" />
 
|}
 
|}
 +
<references group="EJTAG">
 +
<ref name="jtag">Note that the JTAG function is controlled by {{CI20 GPIO|PA|30}}, and may be turned on by the bootloader - see the [[CI20 Hardware#Programmers Manual|JZ4780 Programmers Manual]]</ref>
 +
</references>
 +
 +
=== Using UART3 ===
 +
By default, the pins that UART3 is exposed on are used for EJTAG. UBOOT needs to be recompiled in order to modify this and you need to have compiled your own kernel from [https://github.com/MIPS/CI20_linux the Ci20 git repository].
 +
 +
Follow the steps [[CI20_Dev_Zone#Building_uboot_from_sources|for building UBOOT from source]], but stop just before running make.
 +
 +
You need to compile UBOOT without support for EJTAG - this is done by editing the following UBOOT file:
 +
 +
vim include/configs/ci20.h
 +
 +
Remove the following line:
 +
 +
#define CONFIG_JTAG
 +
 +
Save the file and continue following the steps for building UBOOT from source.
 +
 +
== Components ==
 +
 +
=== SoC ===
 +
The CI20's SOC is an [[Ingenic JZ4780]] - see the [[CI20 Hardware#SoC Information|data sheet]] and [[CI20 Hardware#Programmers Manual|programmers manuals]] referenced on this page.
 +
 +
=== DDR/RAM ===
 +
Comprises of four H5TQ2G83DFR-H9C (rev A) or K4B2G0846Q-BYK0 (rev B) 2Gbit DDR3 chips, providing 8 bits of data each, providing a 32bit DDR3 memory bus to the SoC clocked at 400MHz
 +
 +
=== ROM/NAND ===
 +
Is provided by a single Samsung K9GBG08UOA NAND flash, using an 8bit data interface to the SoC.
 +
 +
=== Ethernet ===
 +
Is provided by a Davicom DM9000C connected via an 8-bit interface to the SoC, providing 10/100 ethernet.
 +
 +
=== WiFi/BT ===
 +
Is provided by an Ingenic IW8103, based on a Broadcom 4330, connected via SDIO to the SoC's MSC1 port.
 +
 +
=== PMU ===
 +
Is an Active-Semi ACT8600 specifically designed for the Ingenic JZ family of SoCs.
 +
 +
=== RTC ===
 +
Is provided by a Pericom PT7C4337UE connected to the SoC via the I2C_4 bus.
 +
 +
=== Microphone switcher ===
 +
The automatic 4-pin microphone switching/detection is provided by a Fairchild FSA8049 audio jack detection device.
  
=== Test Points ===
+
== Test Points ==
 
Description of the (rather small little silver dot) test points on the board, derived from the schematic.
 
Description of the (rather small little silver dot) test points on the board, derived from the schematic.
  
Line 683: Line 847:
 
|}
 
|}
  
== Components ==
+
== Documentation ==
  
=== SoC ===
+
{{:CI20 Hardware/Documentation}}
Is an [[Ingenic JZ4780]] - see the data sheet and programmers manuals referenced on this page.
 
 
 
=== DDR/RAM ===
 
Comprises of four H5TQ2G83DFR-H9C 2Gbit DDR3 chips, providing 8 bits of data each, providing a 32bit DDR3 memory bus to the SoC. Anybody have details of the standard clock rate?
 
 
 
=== ROM/NAND ===
 
Is provided by a single Samsung K9GBG08UOA NAND flash, using an 8bit data interface to the SoC.
 
 
 
=== Ethernet ===
 
Is provided by a Davicom DM9000C connected vi an 8-bit interface to the SoC, providing 10/100 ethernet.
 
 
 
=== WiFi/BT ===
 
Is provided by an Ingenic IW8103, based on a Broadcom BCM43362/4330, connected via SDIO to the SoC MSC1 port.
 
 
 
=== PMU ===
 
Is an Active-Semi ACT8600 specifically designed for the Ingenic JZ family of SoCs.
 
 
 
=== RTC ===
 
Is provided by a Pericom PT7C4337UE connected to the SoC via the I2C_4 bus.
 
 
 
=== Microphone switcher ===
 
The automatic 4-pin microphone switching/detection is provided by a Fairchild FSA8049 audio jack detection device.
 
  
 
== OTP and MAC address formats ==
 
== OTP and MAC address formats ==
The following data is stored in the JZ4780 OTP ROM/efuse. This data can be accessed from Linux via the sysfs path of
+
The following data is stored in the JZ4780's OTP ROM/efuse. This data can be accessed from Linux via the sysfs path of
 
  <nowiki>
 
  <nowiki>
 
/sys/devices/platform/jz4780-efuse/</nowiki>
 
/sys/devices/platform/jz4780-efuse/</nowiki>
Line 720: Line 862:
 
     uint32 date; /* ISO8601 yyyymmdd format-ish as an int – for instance ‘20140527’d for May 27th 2014 */
 
     uint32 date; /* ISO8601 yyyymmdd format-ish as an int – for instance ‘20140527’d for May 27th 2014 */
 
     char manufacturer[2];  /* ascii 2-character encoding of manufacturer – ‘NP’ == Nopa */
 
     char manufacturer[2];  /* ascii 2-character encoding of manufacturer – ‘NP’ == Nopa */
     unsigned char mac[6]; /* six byte/48bit MAC address strored as 8-bit integers */
+
     unsigned char mac[6]; /* six byte/48bit MAC address stored as 8-bit integers */
 
};</nowiki>
 
};</nowiki>
 +
 +
== Board Revisions and changes ==
 +
 +
=== Revision V2 (current production) ===
 +
This is the current board being sold.
 +
 +
Changes
 +
* The board is now square with more regular mounting holes
 +
* Additional 4 red user LEDs
 +
* Add a reset button
 +
* SD card moved to reduce interference with WiFi and Bluetooth
 +
 +
=== Revision B ===
 +
 +
Changes
 +
* Board is now purple in color
 +
* DRAM part change. Hynix DDR3 H5TQ2G83CFR-H9C to Samsung K4B2G0846Q-BYK0 . No layout change/firmware
 +
* The board ships with a USB Power cable.
 +
* Fix in silk screen boot select and logo.
 +
 +
=== Revision A ===
 +
 +
* Pre-production limited release.
 +
* Part of the developer giveaway.
 +
* Shipped with an international mains psu
 +
 +
== Accessories ==
 +
 +
'''Note: All parts are untested and links are given as a reference for specification only.'''
 +
 +
The following are possible accessories that can be used for the board.
 +
 +
=== USB Serial TTL Adaptor (Raspberry Pi compatible) ===
 +
 +
The onboard serial is 3.3V TTL compatible. The following link is an example part
 +
 +
http://www.digikey.co.uk/product-detail/en/TTL-232R-RPI/768-1204-ND/4382044
 +
 +
=== Power supply ===
 +
 +
==== PSP ====
 +
 +
The CI20 power connector is the same as the one used for the Sony PSP. So a PSP power supply can directly work.
 +
 +
==== USB Power supply ====
 +
Alternatively, you can use a USB-PSP cable with any standard smartphone/tablet USB PSU
 +
 +
* 1A http://www.digikey.co.uk/product-detail/en/VER05US050-BB/1470-2775-ND/5023717
 +
* 2A http://www.digikey.co.uk/product-detail/en/PA-1100-22L/160-2088-ND/4308119
 +
 +
==== USB PSP Power cable ====
 +
 +
* http://www.amazon.com/Data-Power-USB-Cable-Sony-PSP/dp/B000LEFKXC
 +
* http://www.amazon.co.uk/Sony-Data-Transfer-Power-Cable/dp/B000I5XCN4/ref=pd_cp_vg_h__0
 +
* http://www.amazon.co.uk/Komodo%C2%AE-Charger-Cable-Connector-Charging-Black/dp/B00A78NUSO/
 +
 +
Note: There is a lot of variation in these cables and USB power supplies. If your board randomly dies, power supply/cable can be a possible issue.
 +
 +
=== USB WiFi Adapters ===
 +
 +
USB WiFi adapters usually rely on closed source firmware blobs. And in-tree kernel support depends on the actual chipset in them.
 +
 +
Devices with different/same model numbers can have slightly different device id's and chipsets. This makes driver support tricky.
 +
 +
The following devices have been tested.
 +
 +
{| class="wikitable"
 +
! Name
 +
! Chipset
 +
! Firmware
 +
! State
 +
! Notes 3.0.8
 +
! Notes 3.18 +
 +
|-
 +
| CSL WLAN USB ADAPTER 300Mbps. Mod Nr: 22844/20140520SZ001
 +
| Realtec RTL8192SU
 +
| rtlwifi/rtl8712u.bin
 +
| Does not work.
 +
| There is an out of tree driver that 'might' work. Check https://wireless.wiki.kernel.org/en/users/drivers/rtl819x#rtlwifi
 +
| Works (r8712u staging driver)
 +
|-
 +
| Edimax EW-7811Un
 +
| lsusb says RTL8188CUS, Realtec RTL8192CU driver works
 +
| rtlwifi/rtl8192cufw.bin
 +
| Works. Needs kernel recompile. Not yet included in default Debian images
 +
| If driver is compiled in kernel, it might seem like a boot hang. But it's because it is searching for firmware. Either load firmware in kernel too. Or compile driver as module.
 +
| Works
 +
|-
 +
| TP-Link TL-WN822N Version 3.0
 +
| Realtec RTL8192CU
 +
| rtlwifi/rtl8192cufw.bin
 +
| Works. Needs kernel recompile. Not yet included in default Debian images
 +
| If driver is compiled in kernel, it might seem like a boot hang. But it's because it is searching for firmware. Either load firmware in kernel too. Or compile driver as module.
 +
| Works
 +
|}
  
 
{{CI20}}
 
{{CI20}}
[[Category:CI20|Tech Stuff]]
+
[[Category:CI20|Hardware]]

Latest revision as of 07:40, 13 September 2018

This page details the technical specifications and components of the MIPS Creator CI20 development board.

Tech Spec overview

Ethernet RJ45Eth DM9000ButtonHDMIUART 4EJTAGAudio In/Out5V DC InReset buttonUSB EHCI/OHCIUSB OTG HostExpansion 2USB OTG SelectUSB OTG DeviceActivity LEDsSD CardPower LEDIRCameraDDRDDRJZ4780Boot SelExpansion 1View of the top of the Ci20 V2 board
About this image
DDRDDRNANDPMUBT/WiFiAntennaRTCMicrophone SwitcherView of the bottom of the Ci20 V2 board
About this image
Ethernet RJ45Eth DM9000ButtonHDMIUART 4EJTAGAudio In/Out5V DC InUSB EHCI/OHCIUSB OTG HostExpansion 2USB OTG SelectUSB OTG DeviceSD CardPower LEDIRCameraDDRDDRJZ4780Boot SelExpansion 1View of the top of the CI20 board
About this image
DDRDDRNANDPMUBT/WiFiAntennaRTCMicrophone SwitcherView of the bottom of the CI20 board
About this image
Feature Rev A Rev B V2
SoC Ingenic JZ4780
CPU Dual 1.2GHz XBurst MIPS32 little endian
Caches 32kI + 32kD per core, 512K shared L2
RAM 1Gbyte DDR3
NAND 8 Gbyte
SDcard 1x full size slot + 1x slot via secondary expansion header
USB 1x USB otg + 1x USB host
Ethernet 1x 10/100Mbps using Davicom DM9000C controller over 8-bit interface
Wifi IW8103 wifi-? + BT4, built in ceramic aerial
GPU PowerVR SGX540
Video Hardware video decoder up to 1080p60
Display HDMI, up to 2k resolution
Camera ITU645 dedicated connector
GPIO 25 available on headers
SPI 2 ports on primary & secondary expansion header, with 4 chip selects
I2C One port on primary expansion header. Note: i2cdetect incorrectly shows some I2C addresses as full. Despite this, the I2C block works fine.
ADC 7 inputs on secondary expansion header, including 5-wire touch and battery monitoring functions
UART 1 on dedicated UART header, 2 via primary expansion header
Audio Audio in and out via 3.5mm 4-wire connector
JTAG Standard 14-pin MIPS EJTAG header
Transport Stream Interface Via secondary expansion header
Power 5V via 4mm (shield) x 1.7mm (pin) center positive connector
Size Approx 90x95mm
Activity LEDs 4 Activity LEDs
Reset Button Reset Button

Connectors

Connector Schem Name Details
Power MK5 4mm shield x 1.7mm pin 5V centre positive
HDMI J3 Full size HDMI out, including audio support
USB A connector (left) J24 Paralleled with the mini OTG connector (note, they are not separate ports - do not plug into both at once!)
USB A connector (right) J23 From the EHCI host controller block
USB mini-OTG connector J8 Paralleled with the full size A connector next to it.
OTG VBUS jumper JP2 Selects VBUS enabling on OTG port to enable master or slave functionality
Ethernet J11 Standard RJ45 connector, with built in link and activity lights
Audio J9 3.5mm 4-pin (stereo out + mic in), with auto-sense chip to handle both OMTP and CTIA headsets
Button SW1 Boot time selector (see boot selector table). Can also be read from software as GPIO. Note, this is not a reset button!
Reset Button (V2 only) RESET System Reset button
Boot mode selector JP3 Used to choose auto-boot from NAND or SDcard slot, predominantly.
SDcard J13 Full size SDcard slot, can be used for storage and/or direct boot
Camera J6 24-pin DVP camera connector
IR U15 Infrared receiver
LED D5 bi-colour status LED (red/blue), wired to USB power enable line
4 Activity LEDs (V2 only) LED0/1/2/3 Red activity LEDs available via /sys/class/leds/
UART J57 Dedicated 4-pin UART header
Primary expansion connector JP4 26-pin (2x13) 'RPi compatible' 0.1" pitch expansion connector, carrying power, UART, SynchronousSerial, I2C and GPIO functions.
Secondary expansion header J5 Carries 5v and 3.3v power out, transport stream, ADC, GPIO, SynchronousSerial(SPI) and MSC(SDcard) functions
EJTAG J58 Standard MIPS 14pin EJTAG connector

Power

The power connector is a 5V 4mm (shield) x 1.7mm (pin) center positive connector. It takes 5V only. Note that this connection is identical to that of the original Sony PSP, so power cables intended for that console also work for the CI20.

State Current draw @ 5V
Power off 0 mA
Suspended 30 mA
Idle (no devices plugged in, Wi-Fi off) 210 mA
Maximum usage (Ethernet, Wi-Fi, SDcard, CPU, GPU all stressed) 750 - 800 mA
Device Current draw @ 5V
HDMI trace
Wi-Fi - in use 100 mA
Wi-Fi - idle trace with spikes of around 40 mA
Ethernet - in use 150 mA
Ethernet - idle 120 mA
CPU + Memory - in use (compared to idle) 90 mA
SDCard - writing 90 mA
SDCard - reading 60 mA

HDMI

Full sized HDMI connection with audio out support as well. The HDMI block on the JZ4780 supports HDMI v1.4a, and appears to be a Synopsys DesignWare HDMI controller, although this is not documented in the JZ4780 programming manual.

In the 3.18 kernel the code is found at drivers/gpu/drm/jz4780, but seems to live in a more generic form at drivers/gpu/drm/bridge/synopsys/dw-hdmi.c in the mainline kernel.

USB A connector (left)

Paralleled with the mini-OTG connector.

USB A connector (right)

Connected to the EHCI USB controller in the SoC.

USB mini-OTG connector

Is paralleled with the left hand USB A connector - do not plug into both of these at once. Has the OTG VBUS controlled by the jumper next to it.

OTG VBUS jumper

Controls the VBUS for the OTG ports-

Jumper shorted = HOST mode.

Jumper not shorted = Device mode.

Ethernet

10/100 RJ45, connects to the DM9000 chipset.

Audio

Standard 4-pin headset connector, with auto OMTP/CTIA detection (so should work with any standard 4-pin headset).

Button

The button between HDMI and Ethernet is not a reset button - it is boot_select0. Combining this button with JP3, it is possible to boot the Ci20 from USB or MSC0.

Once the kernel has been loaded, the button can be used as a GPIO - it is pin PD17.

In the 3.15 kernel, the GPIO is number 113. You can export the GPIO via

echo 113 > /sys/class/gpio/export

Boot mode selector

See the silkscreen on the board and the section at the end of the JZ4780 programmers manual. Fundamentally you can boot from the on-board NAND or direct off the SDcard without having to press the button during boot. There is also a USB boot function available, but it is not a standard DFU type boot, and requires JZ4780 specific host support.

BOOT_SEL[2:1:0] JP3 Jumper (BOOT_SEL1, PD18) SW1 Button (BOOT_SEL0, PD17) Boot Mode
110 Pins 1 & 2 shorted Not pressed NAND flash at CS1
100 Pins 2 & 3 shorted Not pressed SD Card at MSC1
111 Pins 1 & 2 shorted Pressed USB device
101 Pins 2 & 3 shorted Pressed SD NAND flash at MSC0

SDcard

Standard pinout full sized SD/MMC slot that can be used for direct booting, or for bulk storage (standard MTD support under Linux). It is wired to the MSC0 block in the SoC.

Camera

Closeup of compatible camera
Closeup of back of compatible camera
Camera unit fitted

The camera connector is 24 pin (26 pins on the schematic - two of which are the side ground solder tabs on the connector itself - the actual cable interface is 24 pin), and CMOS DVP 8-bit camera compatible.

The Omnivision OV5640 5Mpixel unit can be used with the CI20 (often labelled FD5640 on the actual part)

The connector installed on the CI20 is 24-PIN 0.5Pitch Bottom Contact FPC Connector

A camera module reported to be working by a community member here

Note Be aware that there are some SMT components directly under where the camera unit sits. If your camera unit has a conductive rear surface then this may short out on the board. Symptoms we have seen include board resets. Please insulate the area either on the PCB or the back of the camera unit to avoid this.

IR

The CI20 has an infrared remote control receiver (part IRM-2638A, carrier frequency 37.9kHz), which is connected to GPIO PE3 for software decoding.

LED

The CI20 board features a dual colour red & blue LED. It is controlled by GPIO PF15, which also controls the USB VBUS supply. When PF15 is high the LED lights red, when PF15 is low it lights blue. Software cannot power off the LED. A simple way to toggle the LED colour is to write to the PFPAT0S & PFPAT0C registers from the U-boot shell, in order to toggle the PF15 GPIO. The following example will toggle the colours rapidly, leading to the LED appearing purple:

while true; do mw.l 0xb0010548 0x8000; mw.l 0xb0010544 0x8000; done

ActivityLEDs

Version 2 of the Ci20 board adds 4 red activity LEDs. These LEDs are exposed via sysfs as described here.

Reset

Version 2 of the Ci20 board adds a system reset button.

Dedicated UART header

Pinout and other functions of the dedicated UART header. This is uart4 of the SoC. Note that uart0 is on the 26pin main expansion header.

pin schematic GPIO 2nd func 3rd func
1 +3v3
2 TXD PC10 LCD_SPL LCD_G0
3 GND
4 RXD PC20 LCD_CLS LCD_R0


Key Power UART4 GPIO LCD

Primary expansion header

Pinout diagram for the main CI20 0.1" pitch 26 pin header

2nd func GPIO schematic pin pin schematic GPIO 2nd func 3rd func 4th func
+3v3 1 2 5V_IN
PD30 I2C1_SDA 3 4 5V_IN
PD31 I2C1_SCK 5 6 GND
UART1_TXD PD28 GPIO1 7 8 UART0_TXD PF3
GND 9 10 UART0_RXD PF0 GPS_CLK
UART1_RXD PD26 GPIO2 11 12 PWM PE5 PWM5 UART3_TXD SCLK_RSTN
UART1_CTS PD27 GPIO3 13 14 GND
UART1_RTS PD29 GPIO4 15 16 GPIO5 PF1 UART0_CTS GPS_MAG
+3v3 17 18 GPIO6 PF2 UART0_RTS GPS_SIG
SSI1_DT PE17 SSI0_DT 19 20 GND
SSI1_DR PE14 SSI0_DR 21 22 GPIO7 PE8 UART3_CTS BCLK_AD
SSI1_CLK PE15 SSI0_CLK 23 24 SSI0_CE0 PE16 SSI1_CE0
GND 25 26 SSI0_CE1 PE18 SSI1_CE1


Key Power UART0 UART1 UART3 SSI
GPS[primary 1] I2C I2S[primary 2] GPIO PWM[primary 3]
  1. Note that the GPS interface is unavailable as it is (believed to be) electrically incompliant
  2. Note that the I2S block is not useable on the header as not all I2S pins are brought out
  3. Note that the PWM facility is unavailable as this PWM unit is used by the Linux kernel SMP timer code

Secondary expansion header

Pinout diagram for the secondary CI20 0.1" pitch 16 pin header

3nd func 2nd func GPIO schematic pin pin schematic GPIO 2nd func 3rd func
+3v3 1 2 5V_IN
TSFRM MSC2_D3 PB31 SSI1_CE0 3 4 SSI1_CLK PB28 MSC2_CLK TSCLK
TSSTR MSC2_CMI PB29 SSI1_DT 5 6 SSI1_DR PB20 MSC2_D0 TSDIO
TSDI1 MSC2_D1 PB21 SSI1_CE1 7 8 SSI1_GPC PB30 MSC2_D2 TSFAIL
XP 9 10 XN
YP 11 12 YN
AUX1 13 14 AUX2
VBAT 15 16 GND


Key Power TSSI ADC GPIO SSI MSC

EJTAG

14-pin MIPS EJTAG headers. See proposed OpenOCD/wiggler support project.

3nd func 2nd func schematic pin pin schematic
TRST_N 1 2 GND
PS2_KCLK UART3_RXD TDI_RXD 3 4 GND
PS2_KDATA UART3_TXD TDO_TXD 5 6 GND
PS2_MDATA UART3_CTS TMS 7 8 GND
PS2_MCLK UART3_RTS TCK 9 10 GND
RST_N 11 12 N/C
N/C 13 14 3V3


Key Power PS2 UART3 EJTAG[EJTAG 1]
  1. Note that the JTAG function is controlled by PA30, and may be turned on by the bootloader - see the JZ4780 Programmers Manual

Using UART3

By default, the pins that UART3 is exposed on are used for EJTAG. UBOOT needs to be recompiled in order to modify this and you need to have compiled your own kernel from the Ci20 git repository.

Follow the steps for building UBOOT from source, but stop just before running make.

You need to compile UBOOT without support for EJTAG - this is done by editing the following UBOOT file:

vim include/configs/ci20.h

Remove the following line:

#define CONFIG_JTAG

Save the file and continue following the steps for building UBOOT from source.

Components

SoC

The CI20's SOC is an Ingenic JZ4780 - see the data sheet and programmers manuals referenced on this page.

DDR/RAM

Comprises of four H5TQ2G83DFR-H9C (rev A) or K4B2G0846Q-BYK0 (rev B) 2Gbit DDR3 chips, providing 8 bits of data each, providing a 32bit DDR3 memory bus to the SoC clocked at 400MHz

ROM/NAND

Is provided by a single Samsung K9GBG08UOA NAND flash, using an 8bit data interface to the SoC.

Ethernet

Is provided by a Davicom DM9000C connected via an 8-bit interface to the SoC, providing 10/100 ethernet.

WiFi/BT

Is provided by an Ingenic IW8103, based on a Broadcom 4330, connected via SDIO to the SoC's MSC1 port.

PMU

Is an Active-Semi ACT8600 specifically designed for the Ingenic JZ family of SoCs.

RTC

Is provided by a Pericom PT7C4337UE connected to the SoC via the I2C_4 bus.

Microphone switcher

The automatic 4-pin microphone switching/detection is provided by a Fairchild FSA8049 audio jack detection device.

Test Points

Description of the (rather small little silver dot) test points on the board, derived from the schematic.

Label Function
TP9 LCD PCLK output
TP72 TEST_TE input
TP10 DRVVBUS
TP8 CLK32K
TP19 BOOT_SEL2 boot mode setting - pulled high to 3.3V with a 10K resistor.
TP20 BOOT_SEL1 boot mode setting - shared with JP3 (the boot mode jumper)
TP21 BOOT_SEL0 boot mode setting - shared with SW1 (the button)
TP24 VDDMEM
TP25 VDDCORE
TP26 +3.3V rail
TP27 +2.5V rail
TP23 VRTC18/WKUP_N through 100K resistor
TP22 VRTC18/RST_N through 200K resistor
TP62 DEVICE_VBUS
TP63 OTG_DM
TP64 OTG_DP
TP65 Ground
TP66 HOST_5V
TP67 USB_DM
TP68 USB_DP
TP69 Ground
TP77 WIFI_IO
TP136 Wifi chip RF_SW_CTRL_3 pin
TP137 Wifi chip RF_SW_CTRL_6 pin

Documentation

The following links provide information (predominantly PDF files) about the SoC, board and components for the MIPS Creator CI20.

SoC Information

Overview on the Imagination web site

JZ4780 pdf datasheet from the Ingenic FTP site

Programmers Manual

JZ4780 pdf programmers manual from vendor file archive

Schematic

Schematic for V1 boards is available here. And for V2 boards here

Board components and identification

Board/component (BOM) identification pdf from the CI20 file archive

DDR chip manual CI20 file archive

Davicom DM9000C Ethernet controller device datasheet

NAND chip manual CI20 file archive

Power Management Unit (PMU) chip manual CI20 file archive

Real Time Clock (RTC) chip manual CI20 file archive

Expander pinouts

Main expander pinout and function diagram pdf from the CI20 file archive (also on Hardware page)

Secondary expander pinout and function diagram pdf from the CI20 file archive (also on Hardware page)

Dedicated UART header pinout and function diagram pdf from the CI20 file archive (also on Hardware page)

EJTAG header pinout and function digram on Hardware page

OTP and MAC address formats

The following data is stored in the JZ4780's OTP ROM/efuse. This data can be accessed from Linux via the sysfs path of

/sys/devices/platform/jz4780-efuse/

The C definition of the actual efuse area data format is:

struct __packed__ otp {
    uint32 serial_number;  /* As a decimal, huge range */
    uint32 date; /* ISO8601 yyyymmdd format-ish as an int – for instance ‘20140527’d for May 27th 2014 */
    char manufacturer[2];  /* ascii 2-character encoding of manufacturer – ‘NP’ == Nopa */
    unsigned char mac[6]; /* six byte/48bit MAC address stored as 8-bit integers */
};

Board Revisions and changes

Revision V2 (current production)

This is the current board being sold.

Changes

  • The board is now square with more regular mounting holes
  • Additional 4 red user LEDs
  • Add a reset button
  • SD card moved to reduce interference with WiFi and Bluetooth

Revision B

Changes

  • Board is now purple in color
  • DRAM part change. Hynix DDR3 H5TQ2G83CFR-H9C to Samsung K4B2G0846Q-BYK0 . No layout change/firmware
  • The board ships with a USB Power cable.
  • Fix in silk screen boot select and logo.

Revision A

  • Pre-production limited release.
  • Part of the developer giveaway.
  • Shipped with an international mains psu

Accessories

Note: All parts are untested and links are given as a reference for specification only.

The following are possible accessories that can be used for the board.

USB Serial TTL Adaptor (Raspberry Pi compatible)

The onboard serial is 3.3V TTL compatible. The following link is an example part

http://www.digikey.co.uk/product-detail/en/TTL-232R-RPI/768-1204-ND/4382044

Power supply

PSP

The CI20 power connector is the same as the one used for the Sony PSP. So a PSP power supply can directly work.

USB Power supply

Alternatively, you can use a USB-PSP cable with any standard smartphone/tablet USB PSU

USB PSP Power cable

Note: There is a lot of variation in these cables and USB power supplies. If your board randomly dies, power supply/cable can be a possible issue.

USB WiFi Adapters

USB WiFi adapters usually rely on closed source firmware blobs. And in-tree kernel support depends on the actual chipset in them.

Devices with different/same model numbers can have slightly different device id's and chipsets. This makes driver support tricky.

The following devices have been tested.

Name Chipset Firmware State Notes 3.0.8 Notes 3.18 +
CSL WLAN USB ADAPTER 300Mbps. Mod Nr: 22844/20140520SZ001 Realtec RTL8192SU rtlwifi/rtl8712u.bin Does not work. There is an out of tree driver that 'might' work. Check https://wireless.wiki.kernel.org/en/users/drivers/rtl819x#rtlwifi Works (r8712u staging driver)
Edimax EW-7811Un lsusb says RTL8188CUS, Realtec RTL8192CU driver works rtlwifi/rtl8192cufw.bin Works. Needs kernel recompile. Not yet included in default Debian images If driver is compiled in kernel, it might seem like a boot hang. But it's because it is searching for firmware. Either load firmware in kernel too. Or compile driver as module. Works
TP-Link TL-WN822N Version 3.0 Realtec RTL8192CU rtlwifi/rtl8192cufw.bin Works. Needs kernel recompile. Not yet included in default Debian images If driver is compiled in kernel, it might seem like a boot hang. But it's because it is searching for firmware. Either load firmware in kernel too. Or compile driver as module. Works