CI20 Hardware
This page details the technical specifications and components of the MIPS Creator CI20 development board.
Contents
- 1 Tech Spec overview
- 2 Files
- 3 Source code
- 4 SDcard images
- 5 Connectors
- 5.1 Overview
- 5.1.1 Power
- 5.1.2 Audio
- 5.1.3 EJTAG
- 5.1.4 Secondary 0.1" expansion header
- 5.1.5 HDMI
- 5.1.6 Button
- 5.1.7 Ethernet
- 5.1.8 Boot mode selector
- 5.1.9 Primary expansion header
- 5.1.10 Camera
- 5.1.11 IR
- 5.1.12 LED
- 5.1.13 SDcard
- 5.1.14 USB mini-OTG connector
- 5.1.15 OTG VBUS jumper
- 5.1.16 USB A connector (left)
- 5.1.17 USB A connector (right)
- 5.1.18 Dedicated UART header
- 5.2 Test Points
- 5.1 Overview
- 6 Components
- 7 OTP and MAC address formats
Tech Spec overview
Feature | Details |
---|---|
SoC | Ingenic JZ4780 |
CPU | Dual 1.2GHz XBurst MIPS32 little endian |
Caches | 32kI + 32kD per core, 512K shared L2 |
RAM | 1Gbyte DDR3 |
NAND | 8Gbytes NOR |
SDcard | 1x full size slot + 1x slot via expansion |
USB | 1xUSB otg + 1xUSB host |
Ethernet | 1x 10/200 |
Wifi | IW8103 wifi-? + BT4, built in ceramic aerial |
GPU | SGX540 |
Video | Hardware video decode upto 1080p60 |
Display | HDMI, upto 2k resolution |
Camera | ITU645 dedicated connector |
GPIO | 23 available on headers |
SPI | 2 ports on headers, with 4 chip selects |
I2C | One port on header |
ADC | 7 inputs on header, including 5-wire touch and battery monitoring functions |
UART | 1 on dedicated header, 2 vi pin headers |
Audio | Audio in and out via 3.5mm 4-wire connector |
JTAG | Standard 14-pin MIPS EJTAG header |
Transport Stream Interface | Via pin header |
Power | 5V via 4mm (shield) x 1.7mm (pin) center positive connector |
Size | Apprx 90x95mm |
Files
The following links provide information (predominantly PDF files) about the SoC, board and components for the MIPS Creator CI20.
SoC Information
Overview on the Imagination web site
English page on the Ingenic web site
FTP download from the Ingenic ftp site
JZ4780 pdf datasheet from the CI20 file archive
Programmers Manual
JZ4780 pdf datasheet from the CI20 file archive
Schematic
Schematic pdf from the CI20 file archive
Board components and identification
Board/component (BOM) identication pdf from the CI20 file archive
DDR chip manual CI20 file archive
Ethernet chip manual CI20 file archive
NAND chip manual CI20 file archive
Power Management Unit (PMU) chip manual CI20 file archive
Real Time Clock (RTC) chip manual CI20 file archive
Expander pinouts
Main expander pinout and function diagram pdf from the CI20 file archive
Secondary expander pinout and function diagram pdf from the CI20 file archive
Dedicated UART header pinout and function diagram pdf from the CI20 file archive
Source code
The source code is hosted on github, and in the process of being upstreamed.
Please see the Dev Zone page for details.
SDcard images
Please see the Downloads page for links to the SDcard images.
Connectors
Overview
Starting with the power connector, going anti-clockwise (ish) as you face the front of the board:
Connector | Schem Name | Details |
---|---|---|
Power | MK5 | 4mm shield x 1.7mm pin 5V centre positive |
Audio | J9 | 3.5mm 4-pin (stereo out + mic in), with auto-sense chip to handle both OMTP and CTIA headsets |
EJTAG | J58 | Standard MIPS 14pin EJTAG connector |
Secondary 0.1" expansion header | J5 | Carries 5v and 3.3v power out, transport stream, ADC, GPIO, SynchronousSerial(SPI) and MSC(SDcard) functions |
HDMI | J3 | Full size HDMI out, including audio support |
Button | SW1 | Boot time selector (see boot selector table). Can also be read from software, and create GPIO interrupt/ Note, this is not a reset button! |
Ethernet | J11 | Standard RJ45 connector, with built in link and activity lights |
Boot mode selector | JP3 | Used to choose auto-boot from NAND or SDcard slot, predominantly. |
Primary expansion connector | JP4 | 26-pin (2x13) 'RPi compatible' 0.1" pitch expansion connector, carrying power, UART, SynchronousSerial, I2C and GPIO functions. |
Camera | J6 | 24-pin DVP camera connector |
IR | U15 | Infrared receiver |
LED | D5 | bi-colour status LED (red/blue), wired to USB power enable line |
SDcard | J13 | Full size SDcard slot, can be used for storage and/or direct boot |
USB mini-OTG connector | J8 | Paralleled with the full size A connector next to it. |
OTG VBUS jumper | JP2 | Selects VBUS enabling on OTG port to enable master or slave functionality |
USB A connector (left) | J24 | Paralleled with the mini OTG connector (note, they are not separate ports - do not plug into both at once!) |
USB A connector (right) | J23 | From the EHCI host controller block |
UART | J57 | Dedicated 4-pin UART header |
Power
The power connector is a 5V 4mm (shield) x 1.7mm (pin) center positive connector. It takes 5V only.
When somebody measures the current draw - maybe add it here?
Audio
Standard 4-pin headset connector, with auto OMTP/CTIA detection (so should work with any standard 4-pin headset).
EJTAG
14-pin MIPS EJTAG headers. See projects for proposed OpenOCD/wiggler support project.
Secondary 0.1" expansion header
Pinout diagram for the secondary CI20 0.1" pitch 16 pin header
HDMI
Full sized HDMI connection with audio out support as well. Can somebody confirm the HDMI version support (1.2a?), and also the number of audio out channels? (2, 5.1 ???).
Button
The button between HDMI and Ethernet is not a reset button.
It is boot_select0. Combined with JP3, it can be used to boot the CI20 from the USB.
It can also be used as a gpio once the CI20 is powered up. The boot_sel0 pin is connected to PD17.
Pinmux options can be checked to see which gpio is PD17 in kernel you booted.
In the 3.15 kernel, the gpio is number 113.
You can export the gpio via
echo 113 > /sys/class/gpio/export
And then use it.
Ethernet
10/100 RJ45, connects to the DM9000 chipset.
Boot mode selector
See the silkscreen on the board and the section at the end of the JZ4780 programmers manual (and can somebody transcribe the silkscreen into this section please...) - fundamentally you can boot from the on-board NAND or direct off the SDcard. There is also a USB boot function available, but it is not a standard DFU type boot, and requires JZ4780 specific host support.
Primary expansion header
Pinout diagram for the main CI20 0.1" pitch 26 pin header
Camera
The camera connector is 24 pin (26 pins on the schematic - two of which are the side ground solder tabs on the connector itself - the actual cable interface is 24 pin), and CMOS DVP 8-bit camera compatible. The Omnivision OV5640 5Mpixel unit can be used with the CI20 (often labelled FD5640 on the actual part)
IR
Receive only. Anybody got details on the protocols supported by hardware, and if pure software can be used to support other protocols?
LED
The CI20 board features a dual colour red & blue LED. It is controlled by GPIO PF15, which also controls the USB VBUS supply. When PF15 is high the LED lights red, when PF15 is low it lights blue. Software cannot power off the LED. A simple way to toggle the LED colour is to write to the PFPAT0S & PFPAT0C registers from the U-boot shell, in order to toggle the PF15 GPIO. The following example will toggle the colours rapidly, leading to the LED appearing purple:
while true; do mw.l 0xb0010548 0x8000; mw.l 0xb0010544 0x8000; done
SDcard
Standard pinout full sized SD/MMC slot. Can be used for direct booting, or for bulk storage (standard MTD support under Linux). Is wired to the MSC0 block in the SoC.
USB mini-OTG connector
Is paralleled with the left hand USB A connector - do not plug into both of these at once. Has the OTG VBUS controlled by the jumper next to it.
OTG VBUS jumper
Controls the VBUS for the OTG ports - would somebody like to describe the difference between having the connector fitted or not please.
USB A connector (left)
Paralleled with the mini-OTG connector.
USB A connector (right)
Connected to the EHCI USB controller in the SoC.
Dedicated UART header
Pinout and other functions of the dedicated UART header. This is uart4 of the SoC. Note that uart0 is on the 26pin main expansion header.
Test Points
Description of the (rather small little silver dot) test points on the board, derived from the schematic.
Label | Function |
---|---|
TP9 | LCD PCLK output |
TP72 | TEST_TE input |
TP10 | DRVVBUS |
TP8 | CLK32K |
TP19 | BOOT_SEL2 boot mode setting - pulled high to 3.3V with a 10K resistor. |
TP20 | BOOT_SEL1 boot mode setting - shared with JP3 (the boot mode jumper) |
TP21 | BOOT_SEL0 boot mode setting - shared with SW1 (the button) |
TP24 | VDDMEM |
TP25 | VDDCORE |
TP26 | +3.3V rail |
TP27 | +2.5V rail |
TP23 | VRTC18/WKUP_N through 100K resistor |
TP22 | VRTC18/RST_N through 200K resistor |
TP62 | DEVICE_VBUS |
TP63 | OTG_DM |
TP64 | OTG_DP |
TP65 | Ground |
TP66 | HOST_5V |
TP67 | USB_DM |
TP68 | USB_DP |
TP69 | Ground |
TP77 | WIFI_IO |
TP136 | Wifi chip RF_SW_CTRL_3 pin |
TP137 | Wifi chip RF_SW_CTRL_6 pin |
Components
SoC
Ia an Ingenic JZ4780 - see the data sheet and programmers manuals referenced on this page.
DDR/RAM
Comprises of four H5TQ2G83DFR-H9C 2Gbit DDR3 chips, providing 8 bits of data each, providing a 32bit DDR3 memory bus to the SoC. Anybody have details of the standard clock rate?
ROM/NAND
Is provided by a single Samsung K9GBG08UOA NAND flash, using an 8bit data interface to the SoC.
Ethernet
Is provided by a Davicom DM9000C connected vi an 8-bit interface to the SoC, providing 10/100 ethernet.
WiFi/BT
Is provided by an Ingenic IW8103, based on a Broadcom BCM43362/4330, connected via SDIO to the SoC MSC1 port.
PMU
Is an active-semo ACT8600 specifically designed for the Ingenic JZ family of SoCs.
RTC
Is provided by a Pericom PT7C4337UE connected to the SoC via the I2C_4 bus.
Microphone switcher
The automatic 4-pin microphone switching/detection is provided by a Fairchild FSA8049 audio jack detection device.
OTP and MAC address formats
The following data is stored in the JZ4780 OTP ROM/efuse. This data can be accessed from Linux via the sysfs path of
/sys/devices/platform/jz4780-efuse/
The C definition of the actual efuse area data format is:
struct __packed__ otp { uint32 serial_number; /* As a decimal, huge range */ uint32 date; /* ISO8601 yyyymmdd format-ish as an int – for instance ‘20140527’d for May 27th 2014 */ char manufacturer[2]; /* ascii 2-character encoding of manufacturer – ‘NP’ == Nopa */ unsigned char mac[6]; /* six byte/48bit MAC address strored as 8-bit integers */ };
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