Check the CI20_MPlayer page for details
An obvious choice to port to the board - with the connectivity, HDMI, hardware video decoder and GPU...
And when XBMC runs, add a direct TSSI (Transport Stream Slave Interface) demod to the expander2?
RPi compat layer
Given that the board has an RPi shaped expansion header, and should be able to run all the RPi code, it should be feasible to make an 'RPi out of the box' image for the board.
Check the following
Once the Android image is out then there should be a plethora of interesting Android based projects ...
"Iris is an operating system based on a capability microkernel. It runs on Ingenic JzSoc devices, such as the NanoNote." Maybe port this (native) Jz OS to the CI20 : http://projects.qi-hardware.com/index.php/p/iris/
It should be perfectly feasible to wire a 'wiggler' to the EJTAG connector and get OpenOCD working with the core. It may require some 'work', but hey, isn't that part of the fun?
Use the hardware cursor plane
The JZ4780 has hardware support for a 'cursor plane' which is not presently in use (the cursor is currently done with software) - for raw Linux/X at least. Seeing as the hardware exists, we should try to utilise it under X.
Accelerate 2D X desktop maybe
The JZ4780 has quite a rich display path with a number of accelerators, predominantly aimed at the Android display stack. We should see if we can utilise some of these (like the 2D blitter functions) for X 2D acceleration.
External LCD/touch display via SPI maybe
Could be used to display real time data from cpu etc.Or maybe just for a portable CI20? Or even a handheld gaming console? Here is a RPI equivalent in action(movie + pacman clone):
Here's the description of the LCD "shield" used in above video
Our display modules provide a TFT LCD display, a resistive touchscreen with controller and tactile switches. They are connected over SPI bus and are besides for the Raspberry Pi therefore also suitable for all embedded systems with SPI bus. Especially for ones that do not have a LCD controller or are lacking I/O pins. Our displays only need SPI pins (MISO, MOSI, SCK, SPICS0 and SPICS1) to work.
Utilise the other MIPS cores maybe
As well as having the dual MIPS primary cores, there are two other smaller MIPS cores in the SoC - one in the middle of the video decoder block, and one in the DMA unit. It would probably be fun to run some code on those - and maybe investigate if they can run independent of the main cores so maybe run a small OS (like Contiki etc.) on them doing 'interesting' things in super-low-power modes etc.
There are some references about the VPU MIPS core: https://github.com/laanwj/gcw0_vpu_poc