Embedded Open Modular Architecture/CompactFlash
page under development.
this standard is primarily designed for ultra-low-cost systems as well as those where space is at a premium. because of this, specifying MIPI as the LCD standard would be inappropriate, as indeed would eDP. even in cases where the SoC does not have LVDS, a low-cost RGB/TTL to LVDS IC is available such as the [TI SN75LVDS83b](http://www.ti.com/product/sn75lvds83). so for the low end market, connection to 320x240 (or even smaller) LCDs is directly possible via RGB/TTL, and for the high-end market conversion via LVDS or MIPI ICs is possible on the other side of the interface (e.g. via the [SSD2828](http://www.solomon-systech.com/en/product/display-ic/mipi-master-bridge-chip/ssd2828/).
the edge of the CF card can have as many connectors as will fit into a 43mm width. Micro-HDMI Type D, USB-OTG and a 2.5mm 4-pin Headphone Jack can be considered. A MicroSD slot could be placed on one of the side edges (requiring the module to be removed and switched off in order to access it, as is the case with most mobile phones).
TODO: ensure no clash with power pins http://pinouts.ru/Memory/CompactFlash_pinout.shtml
These pinouts make no attempt to be electrically or electronically compatible with the existing CompactFlash standard. 16 GPIO pins, Single-channel LVDS for LCD, USB2, I2C, 10/100/1000 Ethernet and SATA-II interfaces are included in the Version 1.0 specification. Note: USB2, SATA-II and Ethernet must support auto-negotiation, and must support the lower capabilities (USB 1, USB 1.1, SATA-I, 10/100 Ethernet). Higher speeds and capabilities are optional.
Two 5.0v power inputs must be provided: all pins are rated at 0.5 amps, so the maximum power dissipation is limited to 5 watts. Design consideration: please note that to ensure that thermal dissipation in an enclosed fanless situation is not exceeded, a maximum of 3.5 watts should be respected. Most systems will not have active cooling.
All High-speed signals (USB2, USB3) are balanced lines that are still separated using GND or Power pins. All other pins are low frequency. The sixteen GPIO pins are available, for general-purpose bi-directional use of digital data only.
The typical voltages of the RGB/TTL LCD lines should be compatible with the LVDS output from a Texas Instruments SN75LVDS83b, i.e. 1.25V +/- 0.125V, 5V tolerant, and the peak-to-peak common-mode output voltage around 150mV, as illustrated in Figure 3 of the SN75LVDS83b datasheet.
Also, because the GPIO pins can be reconfigured individually bi-directional for any digital purposes, they *must* be made to be 5V TTL tolerant and tri-state isolated, and Motherboards also must be 5.0v TTL tolerant as well as tri-state isolated. Levels when any GPIO pin is used either as an input or as an output should again operate at nominal 3.3v TTL levels, thus expect "High" Voltage of 2.0 volts, threshold of 1.4v and "Low" voltage of 0.8v.
The maximum LCD Resolution supported must be at least 1366x768 @ 60fps, however there is no restriction on reducing the number of bits per pixel (to 8bpp or even to monochrome) if a particular SoC has severe video bandwidth limitations.
Table of EOMA-CF pinouts
|Row 1||Row 2|
|* 1 LCD Pixel Data bit 3 (Red3)||* 26 LCD Pixel Data bit 4 (Red4)|
|* 2 LCD Pixel Data bit 5 (Red5)||* 27 LCD Pixel Data bit 6 (Red6)|
|* 3 LCD Pixel Data bit 7 (Red7)||* 28 LCD Pixel Data bit 11 (Green3)|
|* 4 LCD Pixel Data bit 12 (Green4)||* 29 LCD Pixel Data bit 13 (Green5)|
|* 5 LCD Pixel Data bit 14 (Green6)||* 30 LCD Pixel Data bit 15 (Green7)|
|* 6 LCD Pixel Data bit 19 (Blue3)||* 31 LCD Pixel Data bit 20 (Blue4)|
|* 7 LCD Pixel Data bit 21 (Blue5)||* 32 LCD Pixel Data bit 22 (Blue6)|
|* 8 LCD Pixel Data bit 23 (Blue7)||* 33 LCD Pixel Clock|
|* 9 GROUND||* 34 GROUND|
|* 10 GPIO (0) / SDMMC-D3||* 35 GPIO (1) / SDMMC-D2|
|* 11 GPIO (2) / UART-TX||* 36 GPIO (3) / UART-RX|
|* 12 GPIO (4) / SDMMC-CMD||* 37 GPIO (5) / SDMMC-CLK|
|* 13 GPIO (6) / SDMMC-D0||* 38 GPIO (7) / SDMMC-D1|
|* 14 I2C Clock (SCL)||* 39 I2C Data (SDA)|
|* 15 GPIO (10) / PWM||* 40 LCD Vertical Synchronization|
|* 16 LCD Horizontal Synchronization||* 41 LCD Pixel data enable (TFT) output|
|* 17 GPIO (12) / SPI_MISO||* 42 GPIO (13) / SPI_MOSI|
|* 18 GPIO (14) / SPI_SCK||* 43 GPIO (15) / SPI_CS|
|* 19 ---- not used ---- / USB3 StdA_SSRX-||* 44 ---- not used ---- / USB3 StdA_SSRX+|
|* 20 ---- not used ---- / USB3 StdA_SSTX-||* 45 ---- not used ---- / USB3 StdA_SSTX+|
|* 21 USB2 (Data-)||* 46 USB2 (Data+)|
|* 22 PWR (5.0V)||* 47 PWR (5.0v)|
|* 23 GPIO (11) / EINT0||* 48 VREF-TTL (GPIO TTL Voltage Reference)|
|* 24 GROUND||* 49 GROUND|
|* 25 2nd USB2 (Data+)||* 50 2nd USB2 (Data-)|
Example CPU Card
This example CPU Card shows what is possible. It comprises an Allwinner A10 (Cortex A8), 2 DDR RAM ICs, 2 NAND Flash ICs, an AXP209 PMIC, an RTL8120 10/100 Ethernet PHY, yet leaves enough room for Micro-HDMI, USB-OTG and a Headphone socket. Missing from this diagram is where to put a MicroSD slot (hence the "under development" sign on this page). Potentially it could go on the underneath side (BOTTOM).
Prevention of insertion of standard CF Cards
To stop EOMA/CF cards from being inserted into standard CF slots, it will probably be necessary for the EOMA/CF cards to be a little bit thicker than standard CF cards, and potentially slightly wider at the very end (nearest the sockets). This would limit the number of sockets that could be used, however examination of some of 3M's sockets shows that the ejector mechanism is only down one side.