Difference between revisions of "Embedded Open Modular Architecture/EOMA-200"
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Revision as of 09:08, 6 April 2013
- 1 EOMA-200
- 2 Introduction
- 3 Design Considerations and suitable CPUs
- 4 Preliminary pinouts
- 5 Interface Negotiation considerations
- 6 Example EOMA-200 PC
- 7 References
- Target uses: Mass-volume retail products. Examples: Small Desktop systems, Micro servers, Smart NAS Home Servers, Digital Signage, Industrial PCs, Education and R&D purposes.
- Dimensions: 100mm x 65mm PCB in a 103 x 68 x 16mm case
- Pinouts: 4 50-pin B2B connectors providing 200 mandatory pins
- Extensibility: 30mm x 14mm front-facing panel space and 2nd 65mm x 14mm front-facing panel
- Power provision: 5V @ 3.5A and 3.3V @ 3.5A (29 Watts total)
With many standards providing 200 or more pins, the differentiator which makes EOMA-200 worthwhile is that all other standards are bare PCB factory-only modules with optional sizes and optional functions. These factors combine to make other standards realistically installable only by experts or technical engineers with knowledge of ESD precautions and the full details of the available options.
The EOMA-200 modular standard is designed to be user-installable in mass-volume appliances. There are no options on the pinouts, thus making the purchasing decisions and the installation easy for the average person. Instead, options for extensibility are offered via two front-facing panels, in exactly the same way that standard ITX and ATX motherboards provide a standard front-facing area. One is of size 30mm x 14mm, and the other is of size 65mm x 14mm. The 65mm panel is sufficient to fit up to 4 Ethernet ports, or up to 8 USB2/3 ports, an HDMI connector, eSATA etc. The 30mm panel is intended but not limited to having an on-board MiniPCIe slot behind it, such that WIFI SMA connectors can be put into the 30mm panel.
Design Considerations and suitable CPUs
As the power provision is for up to 30 Watts, and the PCB size is 100 x 65mm, this standard is suitable for some low-power Intel CPUs, AMD's Fusion chipsets, VIA Nano CPUs and even RDC's IAD100PE offering , as well as the more modern ARM and MIPS SoCs. Designers should note however that provision of PCI Express is MANDATORY, ruling out many of the lower-cost SoCs and those that are targetted at tablets or phones.
The NVidia Tegra 3  is ideally suited to this form-factor, as it has PCI-Express. Although the Tegra 3 does not have Gigabit Ethernet it has a General-purpose memory controller that can take either a DM9000 which provides a 10/100 PHY in a single chip  or an AX88180 [hands.com/~lkcl/eoma/jz4760/AX88180_datasheet.pdf] in combination with an RGMII PHY. The other option for the Tegra 3 is to use a standard PCI-Express Bridge IC and standard PCI Express Gigabit Ethernet ICs.
AMD Fusion CPUs
AMD's Fusion CPUs are also ideally suited, such as the Embedded R-Series including the R-452L, R-260H alongside the A70M or A75 controller hubs . The older G-Series would also be suitable all the way up to the T56N, in combination with the A50M or A55E controller hub  if the lack of USB3 and down-level negotiation to USB2 would be acceptable to end-users, or if a PCI-Express Bridge IC and a standard PCI Express USB3 IC is deployed on the Module's PCB.
Total pinouts summary
These pinouts are NOT OPTIONAL. However, within the majority of the interfaces is the ability to down-level negotiate or provide less than the full set of functionality. For example: if a particular SoC or CPU does not have USB3, then the USB3 pins can be left out and USB2 only provided. Additionally, if a particular low-cost SoC or CPU does not have a full set of 5 USB ports, a Hub Controller IC MUST be deployed on the Module PCB in order to comply with the standard. Likewise for PCIe: if a particular SoC or CPU does not have full 4-lane PCI Express capability then a 2x or even a 1x lane can be provided. Likewise also for the SD/MMC which can reduce down as far as 4 pins (in SPI mode); I2S as well can reduce down to 5 pins; Ethernet can down-level negotiate to 100mb/sec or even 10mb/sec.
HDMI: 12 USB3 (1): 6 USB3 (2): 6 USB3 (3): 6 USB2 (4): 2 USB-OTG (5): 3 SATA: 4 I2C 0: 2 I2C 1: 2 I2S: 8 5V : 8 3.3V : 6 GND: 21 RGB/TTL: 28 SDMMC 1: 12 SDMMC 2: 12 SPI: 4 PCIe4x: 20 Gig Eth: 8 GPIO: 24 UART 1: 2 UART 2: 4 ----- Total: 200
- PCI Express pinouts: 
- SD/MMC description of 4-pin SPI mode: 
- HDMI (Type A) pinouts: 
- SD/MMC: 
- SD/MMC 1-bit, 4-bit and 8-bit modes: 
- eMMC: 
- eMMC pinouts: CMD, CLK, RST, D0-D7. 1 extra pin reserved for Card Detect (if needed)
This block contains HDMI, Ethernet, I2S, I2C, SPI, 8-bit SD/MMC and 6 GPIO. HDMI also has 5 additional GND pins, bringing the total GND pins to 9 for this connector. It also has 3 power pins (2 5V and 1 3.3V)
- 1-12: HDMI (down-level negotiable to DVI)
- 13: GND
- 14-21: Gig Eth (down-level negotiable to 10 or 100mbit/s
- 22: GND
- 23-34: SDMMC 0 (8-bit, down-level negotiable to 4-bit, 1-bit or SPI)
- 35-38: SPI
- 39-40: I2C 1
- 41: GND
- 42-43: 2 5V
- 44: GND
- 45-50: 6 GPIO
Pinouts for Connector 1
|Row 1||Row 2|
|* 1 HDMI Data2+||* 26 SDC0-D0|
|* 2 HDMI Data2-||* 27 SDC0-D1|
|* 3 HDMI Data1+||* 28 SDC0-D2|
|* 4 HDMI Data1-||* 29 SDC0-D3|
|* 5 HDMI Data0+||* 30 SDC0-D4|
|* 6 HDMI Data0-||* 31 SDC0-D5|
|* 7 HDMI Clock+||* 32 SDC0-D6|
|* 8 HDMI Clock-||* 33 SDC0-D7|
|* 9 HDMI CEC||* 34 SDC0-DET (GPIO)|
|* 10 HDMI SCL||* 35 SPI-CS0|
|* 11 HDMI SDA||* 36 SPI-CLK|
|* 12 HDMI HPD||* 37 SPI-MOSI|
|* 13 GND||* 38 SPI-MISO|
|* 14 ---- not used ---- / 1000 Eth BI_DD+||* 39 I2C1_SDA|
|* 15 ---- not used ---- / 1000 Eth BI_DD−||* 40 I2C1_SCL|
|* 16 10/100 Ethernet (RX+) / 1000 Eth BI_DB+||* 41 GND|
|* 17 10/100 Ethernet (RX−) / 1000 Eth BI_DB−||* 42 5.0V|
|* 18 10/100 Ethernet (TX+) / 1000 Eth BI_DA+||* 43 5.0V|
|* 19 10/100 Ethernet (TX−) / 1000 Eth BI_DA−||* 44 GND|
|* 20 ---- not used ---- / 1000 Eth BI_DC+||* 45 GPIO 0|
|* 21 ---- not used ---- / 1000 Eth BI_DC−||* 46 GPIO 1|
|* 22 GND||* 47 GPIO 2|
|* 23 SDC0-RST||* 48 GPIO 3|
|* 24 SDC0-CLK||* 49 GPIO 4|
|* 25 SDC0-CMD||* 50 GPIO 5|
- HDMI is a Type A 
- HDMI 5V Power (DDC) is provided by motherboard
- HDMI can down-level negotiate to DVI by leaving out the CEC pin 
This connector is primarily for PCI Express. 4 of the 6 GPIOs are dedicated to PCI Express management, and the I2C lane is also intended for connection to the PCI Express bus. Also provided is SD/MMC. There are 7 GND pins in total on this connector, four 3.3v and one 5.0V power pins.
- 1-23: PCIe4x + 5 GND
- 24-25: I2C 0
- 26-37: SDMMC 1 (8-bit)
- 39: 1 5.0V
- 40-43: 4 3.3V
- 44: GND
- 45-50: 6 GPIO (GPIO0, GPIO1, PRSNT1, WAKE, PWRGD, PRSNT2)
Pinouts for Connector 2
|Row 1||Row 2|
|* 1 REFCLK+||* 26 SDC1-D0|
|* 2 REFCLK-||* 27 SDC1-D1|
|* 3 GND||* 28 SDC1-D2|
|* 4 HSIp(0)||* 29 SDC1-D3|
|* 5 HSIn(0)||* 30 SDC1-D4|
|* 6 HSIp(1)||* 31 SDC1-D5|
|* 7 HSIn(1)||* 32 SDC1-D6|
|* 8 GND||* 33 SDC1-D7|
|* 9 HSIp(2)||* 34 SDC1-CMD|
|* 10 HSIn(2)||* 35 SDC1-CLK|
|* 11 HSIp(3)||* 36 SDC1-RST|
|* 12 HSIn(3)||* 37 SDC1-DET (GPIO)|
|* 13 GND||* 38 GND|
|* 14 HSOn(0)||* 39 5.0V|
|* 15 HSOp(0)||* 40 3.3V|
|* 16 HSOn(1)||* 41 3.3V|
|* 17 HSOp(1)||* 42 3.3V|
|* 18 GND||* 43 3.3V|
|* 19 HSOn(2)||* 44 GND|
|* 20 HSOp(2)||* 45 GPIO 6|
|* 21 HSOn(3)||* 46 GPIO 7|
|* 22 HSOp(3)||* 47 GPIO 8 (PRSNT1)|
|* 23 GND||* 48 GPIO 9 (WAKE)|
|* 24 I2C0 SCK||* 49 GPIO 10 (PWRGD)|
|* 25 I2C0 SDA||* 50 GPIO 11 (PRSNT2)|
- PCI-Express optional JTAG is for debugging of PCI-e cards, not for the provision of JTAG to debug the Host CPU. If JTAG is to be provided, it is recommended that either some of the GPIO pins be connected to the PCI Express lanes (and use bit-level emulation of JTAG on the Host CPU), or that an Embedded Controller (such as an STM32F) be dedicated to this (and other) purposes, or an alternative interface (such as USB or I2C) have a converter IC added which can be used.
This connector provides 24-pin RGB/TTL, SATA, 2 UARTs and 6 GPIO pins. It also has 4 GND pins and 2 5V power lines. UART 1 is a 2-pin RS232, whilst UART2 provides TX, RX as well as CTS and RTS.
- 1-28: RGB/TTL
- 29: GND
- 30-33: SATA
- 34: GND
- 35-38: UART 2 (RX/TX and CTS/RTS)
- 39-40: UART 1 (RX/TX)
- 41: GND
- 42-43: 2 5.0V
- 44: GND
- 45-50: 6 GPIO
Pinouts for Connector 3
|Row 1||Row 2|
|* 1 LCD Pixel Data bit 0 (Red0)||* 26 LCD Horizontal Synchronization|
|* 2 LCD Pixel Data bit 1 (Red1)||* 27 LCD Vertical Synchronization|
|* 3 LCD Pixel Data bit 2 (Red2)||* 28 LCD Pixel data enable (TFT) output|
|* 4 LCD Pixel Data bit 4 (Red4)||* 29 GND|
|* 5 LCD Pixel Data bit 5 (Red5)||* 30 SATA-III Transmit (A+)|
|* 6 LCD Pixel Data bit 6 (Red6)||* 31 SATA-III Transmit (A−)|
|* 7 LCD Pixel Data bit 7 (Red7)||* 32 SATA-III Receive (B+)|
|* 8 LCD Pixel Data bit 8 (Green0)||* 33 SATA-III Receive (B−)|
|* 9 LCD Pixel Data bit 9 (Green1)||* 34 GND|
|* 10 LCD Pixel Data bit 10 (Green2)||* 35 UART2 TX|
|* 11 LCD Pixel Data bit 11 (Green3)||* 36 UART2 RX|
|* 12 LCD Pixel Data bit 12 (Green4)||* 37 UART2 CTS|
|* 13 LCD Pixel Data bit 13 (Green5)||* 38 UART2 RTS|
|* 14 LCD Pixel Data bit 14 (Green6)||* 39 UART1 TX|
|* 15 LCD Pixel Data bit 15 (Green7)||* 40 UART1 RX|
|* 16 LCD Pixel Data bit 16 (Blue0)||* 41 GND|
|* 17 LCD Pixel Data bit 17 (Blue1)||* 42 5.0V|
|* 18 LCD Pixel Data bit 18 (Blue2)||* 43 5.0V|
|* 19 LCD Pixel Data bit 19 (Blue3)||* 44 GND|
|* 20 LCD Pixel Data bit 20 (Blue4)||* 45 GPIO 12|
|* 21 LCD Pixel Data bit 21 (Blue5)||* 46 GPIO 13|
|* 22 LCD Pixel Data bit 22 (Blue6)||* 47 GPIO 14|
|* 23 LCD Pixel Data bit 23 (Blue7)||* 48 GPIO 15|
|* 24 LCD Pixel Data bit 18 (Blue2)||* 49 GPIO 16|
|* 25 LCD Pixel Clock||* 50 GPIO 17|
This connector is primarily for USB, although it also provides an 8-bit I2S and 6 GPIO pins. There are also 7 GND pins in total, four 5V power pins and two 3.3V power pins
- 1-7: 1 USB3 + 1 GND
- 8-14: 2 USB3 + 1 GND
- 15-21: 3 USB3 + 1 GND
- 22-24: 4 USB2 + 1 GND
- 25-28: 5 USB-OTG (Tx, Rx, ID) + 1 GND
- 29-36: I2S
- 37: GND
- 38-41: 4 5V
- 42: GND
- 45-50: 6 GPIO
Pinouts for Connector 4
|Row 1||Row 2|
|* 1 USB3_0(Data-)||* 26 USB2_3(Data-)|
|* 2 USB3_0(Data+)||* 27 USB2_3(Data+)|
|* 3 ---- not used ---- / USB3_0 StdA_SSRX-||* 28 GND|
|* 4 ---- not used ---- / USB3_0 StdA_SSRX+||* 29 I2S-MCLK|
|* 5 ---- not used ---- / USB3_0 StdA_SSTX-||* 30 I2S-BCLK|
|* 6 ---- not used ---- / USB3_0 StdA_SSTX+||* 31 I2S-LRCK|
|* 7 GND||* 32 I2S-DI|
|* 8 USB3_1(Data-)||* 33 I2S-DO0|
|* 9 USB3_1(Data+)||* 34 I2S-DO1|
|* 10 ---- not used ---- / USB3_0 StdA_SSRX-||* 35 I2S-DO2|
|* 11 ---- not used ---- / USB3_0 StdA_SSRX+||* 36 I2S-DO3|
|* 12 ---- not used ---- / USB3_0 StdA_SSTX-||* 37 GND|
|* 13 ---- not used ---- / USB3_0 StdA_SSTX+||* 38 5.0 V|
|* 14 GND||* 39 5.0 V|
|* 15 USB3_1(Data-)||* 40 5.0V|
|* 16 USB3_1(Data+)||* 41 5.0V|
|* 17 ---- not used ---- / USB3_0 StdA_SSRX-||* 42 GND|
|* 18 ---- not used ---- / USB3_0 StdA_SSRX+||* 43 3.3V|
|* 19 ---- not used ---- / USB3_0 StdA_SSTX-||* 44 3.3V|
|* 20 ---- not used ---- / USB3_0 StdA_SSTX+||* 45 GPIO 18|
|* 21 GND||* 46 GPIO 19|
|* 22 USBOTG_4(Data-)||* 47 GPIO 20|
|* 23 USBOTG_4(Data+)||* 48 GPIO 21|
|* 24 USBOTG_4(ID)||* 49 GPIO 22|
|* 25 GND||* 50 GPIO 23|
- USB3 pinouts 
- I2S 8 pins: MCLK, BCLK, LRCK, DO0, DO1, DO2, DO3, DI
- Strictly speaking, the USB-OTG ID pin is an analog GPIO, and can be implemented as such if a particular SoC or CPU does not have USB-OTG.
Interface Negotiation considerations
EOMA standards provide "graceful degradation" should a particular CPU or SOC not have the full functionality. This section covers the down-level negotiation for the various interfaces which, by their nature, either provide auto-negotiation at the data level or can degrade gracefully by leaving out some of the pins. The interfaces in EOMA-200 which can down-level negotiate are: I2S; both SD/MMC interfaces; PCI Express; all the USB interfaces; Ethernet, SATA, HDMI and the 24-pin RGB/TTL interface
Also, it is worth reiterating that these interfaces are MANDATORY. Provision of the interfaces can be done using controller or bridge ICs, if a particular SoC does not have the full set of interfaces. It is worth noting however that in picking a particular SoC, the total cost of providing the full set of interfaces including the converter and/or bridge ICs needs to be taken into consideration. Often, an ultra-low-cost SoC may end up being more expensive, price/performance-wise, than a more expensive SoC or CPU which has the full set of interfaces.
If a SoC or CPU does not have 3 USB3 ports, then the provision of USB3 should be prioritised in numerical order (or the USB3 ports should be provided through the deployment of a PCI Express Bridge IC - or the use of a 2nd PCI Express interface if the CPU has one - and a standard PCI Express USB3 IC).
In other words, if the SoC only has one USB3 then this should be allocated to the 1st USB3 port on the module, and the remaining two USB3 ports should be USB2. If the SoC only has two USB3s then the first and second USB3 ports on the module should be USB, with the third being USB2.
Additionally, as noted in earlier sections, the provision of all five (5) USB interfaces is MANDATORY. Each interface can provide up to the full data speed, but if a particular SoC, CPU or its Controller Hub does not have the full 5 USB interfaces, then a suitable USB 4-port Hub IC (such as the FE 1.1) could be deployed, or the use of a PCI Express Bridge IC alongside a PCI Express USB3/2 Hub IC could be deployed. Regardless of the method in which it is achieved, the 5 USB interfaces MUST be provided.
If a particular SoC (or CPU and its associated Controller Hub) has more than 5 USB interfaces then designers may choose to deploy some of those extra interfaces out to one of the two EOMA-200 front panels. Additionally, designers may choose to deploy PCIe Bridge ICs and PCI Express USB Hub ICs in order to provide more USB interfaces on the front panel, or any combination thereof as long as the mandatory requirements to provide 5 USB interfaces on Connector 4 are met.
I2S provides AC97 Audio. However, some Motherboards may deploy Audio ICs which do not support the full capabilities of 8-pin I2S. Under these circumstances, the SoC or CPU and its associated Operating System MUST gracefully degrade, auto-detecting if 5-pin I2S (2-channel output and audio in only) or only 4-pin I2S (audio output only) is deployed.
To aid in the discovery of the Audio capabilities, an I2C EEPROM at a known address (TBD) will be available on I2C-0, which will store Linux kernel "Device Tree" data advising of the Motherboard's Audio IC and its capabilities.
All EOMA-200 modules are required to support the full auto-negotiation capabilities of Ethernet, up to the maximum speed chosen to be provided. Specifically:
- Providing 10 Mbit/s Ethernet is acceptable
- Providing 100 Mbit/s Ethernet and down-negotiation to 10 Mbit/s Ethernet is acceptable
- Providing 100 Mbit/s Ethernet only is not acceptable
- Providing 1,000 Mbit/s Ethernet is acceptable as long as down-level negotiation to both 100 Mbit/s and 10 Mbit/s is also provided
- Providing 1,000 Mbit/s Ethernet only is not acceptable.
I/O Boards (devices) must also support up to a maximum chosen Ethernet specification and all speeds below. This guarantees that any Module will work with any I/O Board, with any combination auto-negotiating to the maximum possible speed.
If a particular SoC does not have Ethernet capabilities, then Ethernet MUST still be provided. This can be done in any form, depending on the SoC. The Tegra 3 for example has a General-Purpose Memory Bus, to which PHY ICs such as the DM9000 or GPMB-to-RGMII converter ICs such as the AX88100 can be connected. Another alternative is to use USB-to-Ethernet ICs or PCI Express Ethernet PHY ICs. Regardless of the method chosen, the provision of Ethernet in EOMA-200 is MANDATORY.
Additionally, if a particular SoC or CPU and its associated Controller Hub have additional Ethernet ports, designers may choose to deploy them via one of the two front panels of EOMA-200. Designers may also choose to add in converter or bridge ICs which add extra interfaces anyway, however in doing so it is imperative that the MANDATORY requirements of EOMA-200 be met as well.
- All EOMA-200 Modules MUST provide at least one lane of PCI-e. The remaining PCI-e lanes - up to 2x and 4x - are OPTIONAL, but are recommended.
- If a particular SoC or CPU supports higher speed PCI Express (Gen 3 etc.) then lower speed generations of PCI Express MUST also be supported.
- A module may choose to internally deploy more than one PCIe interface (e.g. to an on-board Mini-PCIe card). However in doing so, compliance with EOMA-200's requirement to provide at least one lane of PCI-e via Connector 2 MUST be met.
If a particular SoC or CPU with its associated Controller Hub does not have PCI Express, then there are a number of options available in order to comply with the EOMA-200 Standard. One is the use of the PLX Tech USB2380 IC  which is a USB2 client to PCI Express (1x PCI-e Gen 1 compatible). If the SoC, CPU (or its Controller Hub) has USB3, then the PLX Tech USB3380  or the USB3382  may be deployed.
However: regardless of how the requirements are met to provide PCI Express, the deployment of these converter ICs MUST NOT be done at the expense of non-compliance with the EOMA-200 mandatory interface requirements. For example: if a USB interface is used to perform USB-to-PCIe conversion, but there are not enough USB interfaces left on the SoC to comply with the mandatory EOMA-200 USB requirements, then an additional USB Hub IC MUST' be deployed on the module in order to meet both the PCI Express and the USB EOMA-200 interface requirements.
All EOMA-200 Modules are required to support the full backwards-compatible auto-negotiation capabilities of SATA, up to the maximum speed and capabilities chosen to be provided. Specificially:
- Provision of SATA-II is acceptable, but provision of SATA-II with only support for 3 Gbit/s SATA-II i.e. no support for all lower speeds is not acceptable.
- Provision of SATA-III is acceptable, provided that backwards-compatibility with all prior versions of SATA are also provided.
If a particular SoC or CPU and its associated Hub Controller IC do not provide SATA, then bridge and/or converter ICs MUST be deployed in order to comply with the EOMA-200 standard. For example, the JM20329  is a highly cost-effective USB2-to-SATA-II solution, and the TI USB3 to SATA bridge IC [www.ti.com/lit/ds/symlink/tusb9260.pdf TUSB9260] is also effective; there exist other options including PCI Express Bridge ICs and USB3-to-SATA-III converter ICs.
Additionally, if a particular SoC or CPU and associated Hub Controller IC has more than one SATA interface, designers may choose to deploy spare SATA interfaces in the form of an on-board mSATA module, or to provide one or more eSATA connectors via the front panel slots of the EOMA-200 standard. Regardless of the design offered, the provision of SATA is MANDATORY, and any provision of such additional functionality MUST NOT be at the detriment of compliance with the EOMA-200 mandatory pinouts.
The RGB/TTL output is the one point where close attention has to be paid on the part of the CPU Card designers, because of the variance between devices in which the CPU Cards will be plugged. This will need careful monitoring and may warrant a "Certification Programme" to ensure that CPU Cards are compliant with a wide range of devices.
- RGB/TTL is a parallel data bus, potentially running at up to 125 or even 150mhz. Both CPU Cards and I/O Boards must ensure that the length of the tracks leading to and from Connector 3 are all of equal length. It is recommended that both the source (e.g the CPU) and the sink (e.g an LVDS IC) are placed as close to the 68-pin connector as possible.
- CPU Cards must provide software-programmable support for anywhere between 190x120 RGB-TTL resolutions all the way up to the maximum that they are capable of, with the maximum resolution being clearly marked on both the CPU Card, as well as the retail packaging in which it is sold.
- CPU Cards should support up to at least 1920x1080 at at least 50fps. However, some ultra-low-cost SoCs, especially those designed for mobile devices, only support up to XGA or WXGA resolutions. The use of such SoCs is not entirely recommended.
- EOMA-200's RGB/TTL interface is 24-bit-wide. If a particular SoC only has e.g. 18-bit or 15-bit RGB/TTL then the LSB (lower) bits must be set to logic output level 0 when the LCD interface is enabled: they must NOT be left floating or tri-state. This ensures that devices which are expecting the full 24-bits do not receive noise on the lower bits of each of the R,G and B 8-bit inputs.
Although there is no reason why individual devices should not have more than one LCD screen, allowing them to be selected, the burden of complexity for screen selection is placed onto the CPU Card software, so any company planning such a multi-screen device over the 24-pin RGB/TTL interface should contact the authors of the EOMA-200 specification (email@example.com). Realistically, however, multi-screen devices should consider using USB-based screen driver technoloy such as that from DisplayLink, or add extra HDMI, DVI, DisplayPort or MIPIport interfaces via one of the two EOMA-200 front panels.
The HDMI Interface is of Type A (4 Differential LVDS pairs) rather than Type B (7 differential pairs). HDMI is however merely an extension of DVI-D, with the addition of CEC. If therefore a particular low-cost SoC does not have an HDMI output, then one possibility is to convert its RGB/TTL output (if available) into DVI, using for example a TI TFP410  converter IC. A better possibility however is for the Module to deploy a PCI Express Bridge IC (or to use a 2nd PCIe interface if it has one) and to deploy a suitable low-power GPU (Graphics IC) which has an HDMI output.
Either way, although the provision of HDMI is MANDATORY in EOMA-200, the provision of DVI-D only (by leaving out the CEC interface) is both reasonable and acceptable for low-cost Modules.
The SD/MMC standard has been extended numerous times, and is backwards-compatible all the way to 4-pin SPI. EOMA-200 modules may therefore provide any version of the SD/MMC standard, but in doing so they must support ALL down-level compatible versions of SD/MMC (including 4-pin SPI interoperability). This requirement is to ensure that smaller low-cost motherboards which only connect some of the pins can still interoperate, as well as support user peripherals that only have the lower levels and data rates.
The uses to which any of the two SD/MMC interface can therefore be put includes, but is not limited to:
- SD/MMC card slots (1-pin, 4-pin and 8-pin data lines)
- eMMC NAND Flash chips
- SD/MMC WIFI modules (removable as well as SIP embedded modules)
- SD/MMC 3G modules and other peripherals
If in the instance that a particular SoC or CPU (with its associated Controller Hub IC) does not have two SD/MMC interfaces, then they MUST still be provided: the interfaces of EOMA-200 are MANDATORY. One method by which a particular SoC may provide SD/MMC is to use a USB-to-SDMMC converter IC (e.g. SMSC's USB224x or USB225x ) or a PCI Express Bridge IC and a PCI Express SD/MMC Controller IC (such as the JMB387 ).
If a particular SoC or CPU has more SD/MMC interfaces than the EOMA-200 standard requires, then designers may choose to deploy an SD/MMC card slot via one of the two EOMA-200 front panel holes, or may choose to add on-board eMMC or other SD/MMC peripherals, soldered to the PCB. Alternatively, designers may choose to deploy USB or PCIe or other converter / bridge ICs to add extra functionality. Regardless of whether these or any other options are explored by the designers, the designers are free to add whatever they choose as long as the EOMA-200 requirements that 2 SD/MMC interfaces are provided, as EOMA-200's interfaces are MANDATORY.
Example EOMA-200 PC
The example below shows how a small Desktop PC can be created. This example has:
- HDMI output
- 1 USB3
- 4 USB2
- 2 Gigabit Ethernet
- 1 eSATA
- Mini PCIe with a combined Bluetooth 4 and 802.11N 300mb/sec WIFI card
- Standard Audio connectors
- DC Power input jack