Difference between revisions of "Embedded Open Modular Architecture/EOMA-26"
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− | === Table of EOMA- | + | === Table of EOMA-26 pinouts === |
{|cellpadding="2" cellspacing="0" border="1" width="60%" | {|cellpadding="2" cellspacing="0" border="1" width="60%" | ||
!style="width:50%"|Row 1 | !style="width:50%"|Row 1 | ||
!style="width:50%"|Row 2 | !style="width:50%"|Row 2 | ||
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− | |* 1 RIN 0- Negative LVDS differential data output | + | |* 1 GROUND |
− | + | |* 14 RIN 0- Negative LVDS differential data output | |
|- | |- | ||
− | |* 2 | + | |* 2 USB2 (Data-) |
− | |* | + | |* 15 RIN 1+ Positive LVDS differential data output |
|- | |- | ||
− | |* 3 RIN | + | |* 3 USB2 (Data+) |
− | + | |* 16 RIN 1- Negative LVDS differential data output | |
|- | |- | ||
− | |* 4 | + | |* 4 PWR (5.0V) |
− | |* | + | |* 17 RIN 2+ Positive LVDS differential data output |
|- | |- | ||
− | |* 5 | + | |* 5 GPIO2 / UART_TX |
− | |* | + | |* 18 RIN 2- Negative LVDS differential data output |
|- | |- | ||
− | |* 6 | + | |* 6 GPIO3 / UART_RX |
− | |* | + | |* 19 PWR (5.0V) |
|- | |- | ||
− | |* 7 | + | |* 7 I2C Clock (SCL) |
− | |* | + | |* 20 SDC-CMD |
|- | |- | ||
− | |* 8 | + | |* 8 I2C Data (SDA) |
− | |* | + | |* 21 SDC-CLK |
|- | |- | ||
− | |* 9 | + | |* 9 GPIO0 |
− | |* | + | |* 22 GPIO4 / SDC-3 |
|- | |- | ||
− | |* 10 | + | |* 10 GPIO1 |
− | |* | + | |* 23 GPIO5 / SDC-2 |
|- | |- | ||
− | |* 11 | + | |* 11 CLKIN+ Positive LVDS differential clock output |
− | |* | + | |* 24 GPIO6 / SDC-1 |
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− | |* 12 | + | |* 12 CLKIN- Negative LVDS differential clock output |
− | |* | + | |* 25 SDC-0 |
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− | |* 13 | + | |* 13 RIN 0+ Positive LVDS differential data output |
− | + | |* 26 GND | |
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Revision as of 13:27, 29 June 2013
Table of EOMA-26 pinouts
Row 1 | Row 2 |
---|---|
* 1 GROUND | * 14 RIN 0- Negative LVDS differential data output |
* 2 USB2 (Data-) | * 15 RIN 1+ Positive LVDS differential data output |
* 3 USB2 (Data+) | * 16 RIN 1- Negative LVDS differential data output |
* 4 PWR (5.0V) | * 17 RIN 2+ Positive LVDS differential data output |
* 5 GPIO2 / UART_TX | * 18 RIN 2- Negative LVDS differential data output |
* 6 GPIO3 / UART_RX | * 19 PWR (5.0V) |
* 7 I2C Clock (SCL) | * 20 SDC-CMD |
* 8 I2C Data (SDA) | * 21 SDC-CLK |
* 9 GPIO0 | * 22 GPIO4 / SDC-3 |
* 10 GPIO1 | * 23 GPIO5 / SDC-2 |
* 11 CLKIN+ Positive LVDS differential clock output | * 24 GPIO6 / SDC-1 |
* 12 CLKIN- Negative LVDS differential clock output | * 25 SDC-0 |
* 13 RIN 0+ Positive LVDS differential data output | * 26 GND |