Embedded Open Modular Architecture/PCMCIA

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Revision as of 14:36, 5 September 2011 by Lkcl (talk | contribs) (add mechanical interoperability section)
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PCMCIA form-factor Open Modular Architecture

This page describes the specification for re-purposing of the PCMCIA interface and form-factor as a portable Embedded Computing Module. Mass-volume "Lowest Common Denominator" interfaces have been chosen, all of which have existed for over a decade, but are low-power enough to be standard across virtually all mass-produced powerful Embedded CPUs. These interfaces are: 24-pin RGB/TTL (for LCD Panels), I2C, USB2, 10/100 Ethernet, and SATA-II. The interfaces have been specifically chosen because they are either essential or they are multi-purpose buses. The only interface which is not particularly common on mass-produced powerful Embedded CPUs is SATA-II: this can be constructed from a USB-to-SATA converter IC such as the Genesys Logic GL831A.

Pinouts (Version 1.0)

These pinouts make no attempt to be electrically or electronically compatible with the legacy PCMCIA standard. 16 GPIO pins, 24-pin RGB/TTL, USB2, I2C, 10/100 Ethernet and SATA-II interfaces are included in the Version 1.0 specification.

Two 5.0v power inputs must be provided: all pins are rated at 0.5 amps, so the maximum power dissipation is limited to 5 watts. This limit is deliberate, to ensure that thermal dissipation in an enclosed fanless situation is not exceeded.

All High-speed signals (USB2, Ethernet, SATA-II) are balanced lines that are still separated using GND pins. All other pins are low frequency, with the exception of the LCD Pixel Clock and Pixel Data pins, which could go as high as 125mhz for 1920x1080 @ 60fps (not recommended). The sixteen GPIO pins are available, for general-purpose use.

  1. LCD Pixel Clock
  2. LCD Pixel data enable (TFT) output
  3. LCD Horizontal Synchronization
  4. LCD Vertical Synchronization
  5. LCD Pixel Data bit 0 (Red0)
  6. LCD Pixel Data bit 1 (Red1)
  7. LCD Pixel Data bit 2 (Red2)
  8. LCD Pixel Data bit 3 (Red3)
  9. LCD Pixel Data bit 4 (Red4)
  10. LCD Pixel Data bit 5 (Red5)
  11. LCD Pixel Data bit 6 (Red6)
  12. LCD Pixel Data bit 7 (Red7)
  13. LCD Pixel Data bit 8 (Green0)
  14. LCD Pixel Data bit 9 (Green1)
  15. LCD Pixel Data bit 10 (Green2)
  16. LCD Pixel Data bit 11 (Green3)
  17. LCD Pixel Data bit 12 (Green4)
  18. LCD Pixel Data bit 13 (Green5)
  19. LCD Pixel Data bit 14 (Green6)
  20. LCD Pixel Data bit 15 (Green7)
  21. LCD Pixel Data bit 16 (Blue0)
  22. LCD Pixel Data bit 17 (Blue1)
  23. LCD Pixel Data bit 18 (Blue2)
  24. LCD Pixel Data bit 19 (Blue3)
  25. LCD Pixel Data bit 20 (Blue4)
  26. LCD Pixel Data bit 21 (Blue5)
  27. LCD Pixel Data bit 22 (Blue6)
  28. LCD Pixel Data bit 23 (Blue7)
  29. GROUND
  30. GROUND
  31. 10/100 Ethernet (TX+)
  32. 10/100 Ethernet (TX-)
  33. 10/100 Ethernet (RX+)
  34. 10/100 Ethernet (RX-)
  35. GROUND
  36. GROUND
  37. USB2 (Data+)
  38. USB2 (Data-)
  39. GROUND
  40. GROUND
  41. I2C Clock (SCL)
  42. I2C Data (SDA)
  43. PWR (5.0V)
  44. PWR (5.0v)
  45. GPIO (0)
  46. GPIO (1)
  47. GPIO (2)
  48. GPIO (3)
  49. GPIO (4)
  50. GPIO (5)
  51. GPIO (6)
  52. GPIO (7)
  53. GPIO (8)
  54. GPIO (9)
  55. GPIO (10)
  56. GPIO (11)
  57. GPIO (12)
  58. GPIO (13)
  59. GPIO (14)
  60. GPIO (15)
  61. GROUND
  62. GROUND
  63. SATA-II Transmit (A+)
  64. SATA-II Transmit (A-)
  65. GROUND
  66. GROUND
  67. SATA-II Receive (B+)
  68. SATA-II Receive (B-)

Start-up procedure

It is required that all pins be disabled (floating tri-state) with the exception of the I2C Bus, the 5.0v Power and Ground Pins 39 and 40. I2C Bus Master is then enabled, to search for an I2C EEPROM. This EEPROM contains Linux Kernel "Device Tree" data, which specifies the devices available on the motherboard, as well as the actual pin-outs. The exact format of the EEPROM data is yet to be decided.

One important aspect of reading the I2C EEPROM is that the CPU card can then correctly access and initialise on-board devices. It also defines the purpose and use of the GPIO pins (if any are required). Also, the format of the LCD data is specified. For example, the pinout diagram on this page assumes 24-pin RGB TTL, but some motherboards may have LCD panels which only have an 18-pin RGB/TTL interface. The data in the I2C EEPROM therefore provides clear specifications on all the motherboard's peripherals.

Future Versions

With the exception of Pins 39 to 44 (5.0v Power, I2C and 2 Ground Pins), all other pins must be tri-state floating in order that future versions of this standard can provide faster (or merely alternative) interfaces. At the time of writing (2011), the interfaces in the 1.0 Specification are "Lowest Common Denominator" yet are still present across the majority of 2011's powerful embedded SoCs (OMAP4440, Enyxos4210, AML-8726-M etc.) However, in the future, the "Lowest Common Denominator" could well comprise MIPI instead of RGB/TTL, SATA-III instead of SATA-II, 2 lane PCI-express (or its successor), USB-3 instead of USB-2 (perhaps even a faster version of ULPI) and Gigabit Ethernet instead of just 10/100. As of 2011 however, the total number of Embedded CPUs supporting all these interfaces and still keeping to a 1.5 watt budget is precisely zero.

Deliberate Mechanical Non-interoperability

The re-use of the PCMCIA standard pinouts with no electrical or electronic compatibility therefore requires mechanical means to ensure that newer cards cannot be inserted into legacy sockets. The proposed solution is therefore to deploy a fascia plate on the PCMCIA card that is both larger in width than the standard 55mm as well as recessed by some 8mm, along the length of one of the 85mm edges. The exact dimensions are yet to be determined, as specific PCMCIA housings need to be examined to ensure that one side can take the recessed "edge stop".