Jetson/AGX Xavier Update Pinmux Manually

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Revision as of 19:32, 26 November 2018 by Peter Pan (talk | contribs) (Created page with "==Get Pin Name== Check [https://developer.nvidia.com/embedded/dlc/jetson-xavier-pinmux Jetson AGX Xavier Pinmux] to get "Device Tree Pin Name" and "Ball Name" by searching "Si...")
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Get Pin Name

Check Jetson AGX Xavier Pinmux to get "Device Tree Pin Name" and "Ball Name" by searching "Signal Name". "Device Tree Pin Name" is used to get current pinmux register setting and "Ball Name" is used to analyze the setting.

 I2S2 has four pins: I2S2_{CLK,DOUT,DIN,FS}, by searching Jetson AGX Xavier Pinmux, we can get below information:
   "Device Tree Pin Name" : dap2_sclk_ph7, dap2_dout_pi0, dap2_din_pi1, dap2_fs_pi2.
   "Ball Name" : DAP2_SCLK, DAP2_DOUT, DAP2_DIN, DAP2_FS.

Get Current Pinmux Setting

Command "sudo cat /sys/kernel/debug/tegra_pinctrl_reg" prints all pins' pinmux setting.

 For I2S2, get current setting by below command:
   nvidia@jetson-0422418042089:~$ sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep dap2
   Bank: 0 Reg: 0x02434000 Val: 0x00000454 -> dap2_din_pi1
   Bank: 0 Reg: 0x02434008 Val: 0x00000400 -> dap2_dout_pi0
   Bank: 0 Reg: 0x02434010 Val: 0x00001440 -> dap2_fs_pi2
   Bank: 0 Reg: 0x02434018 Val: 0x00001440 -> dap2_sclk_ph7

Analyze Pinmux Setting

Check Xavier Technical Reference Manual to get pinmux register definition by searching "Ball Name". The pinmux register name is like PADCTRL_XXXX_"Ball Name"_[0-9].

 For I2S2, by searching Xavier TRM, we get information as:
   For all four pins, bit 10 indicates it's used as SFIO(1) or GPIO(0).
   For all four pins, bit 1:0 indicates its function when using as SFIO, 0 is I2S2.
 With above information, we find out all four pins are already set as I2S2 function.

Update Pinmux Setting

If current setting is not as expected, refer How to update pinmux to update pinmux setting.