Difference between revisions of "Jetson/TX2 USB"

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(USB-Lane Mapping)
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==USB-Lane Mapping==
 
==USB-Lane Mapping==
 
USB lane mapping information is in TX2 adaptation guide. To change the configuration correctly, you need to notice if plugin-manager is working or not.
 
USB lane mapping information is in TX2 adaptation guide. To change the configuration correctly, you need to notice if plugin-manager is working or not.
 +
Please note that the plugin-manager log is in kernel log for rel-28 and bootloader log for rel-31/32. It means dmesg would not show it after rel-3x.
  
 
  [    0.142498] node /plugin-manager/fragment-500-pcie-config match with board >=3310-1000-500
 
  [    0.142498] node /plugin-manager/fragment-500-pcie-config match with board >=3310-1000-500

Revision as of 18:58, 11 November 2019

The Jetson TX2 Developer Kit added an INA3221 power monitoring chip to the reference carrier board for monitoring the 5V supply. Previous or custom carriers without the chip may need to manually enable USB power in the device tree to gain connectivity.

Patched DTB

You can enable USB simply by updating a file on TX2. First, download and extract the File:Tegra186-tx2-usb-base.tar.gz to your Jetson.

Then, follow the directions from Setting the DTB to boot using this new device tree, tegra186-tx2-usb-base.dtb.

Patching the DTS

If you wish to patch and re-compile your own Device Tree Source (DTS), you can do it by enabling battery_reg option in the source.

First, change the supply with battery_reg using the .dtsi file located at:

  [TX2]
  hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi
  [TX2i]
  hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3489-1000-a00-00.dtsi

Change vbus-2-supply from vdd_usb2_5v to battery_reg. The modifications are as follows:

  pinctrl@3520000 {
     vbus-0-supply = <&vdd_usb0_5v>; 
     vbus-1-supply = <&vdd_usb1_5v>;
     - vbus-2-supply = <&vdd_usb2_5v>;
     + vbus-2-supply = <&battery_reg>; 
     vbus-3-supply = <&battery_reg>; 
     vddio-hsic-supply = <&battery_reg>;
     avdd_usb-supply = <&spmic_sd3>;
     vclamp_usb-supply = <&spmic_sd2>;
     avdd_pll_erefeut-supply = <&spmic_sd2>;
  };

Then, regenerate the DTB and flash with the correct DTB.

Discussion Thread

see https://devtalk.nvidia.com/default/topic/1001771/jetson-tx2/no-usb-support-on-custom-base-carrier-board/


USB-Lane Mapping

USB lane mapping information is in TX2 adaptation guide. To change the configuration correctly, you need to notice if plugin-manager is working or not. Please note that the plugin-manager log is in kernel log for rel-28 and bootloader log for rel-31/32. It means dmesg would not show it after rel-3x.

[    0.142498] node /plugin-manager/fragment-500-pcie-config match with board >=3310-1000-500
[    0.142936] node /plugin-manager/fragment-500-xusb-config match with board >=3310-1000-500
[    0.143213] node /plugin-manager/fragment-500-e3325-pcie match with board >=3310-1000-500

If above plugin-manager log is shown in your dmesg, which means your device has been overwritten again by plugin-manager. Thus, the result of pcie-usb mapping may not be what you want.
Please comment out above three fragment in hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-plugin-manager/
tegra186-quill-p3310-1000-a00-plugin-manager.dtsi(TX2) or tegra186-quill-p3489-1000-a00-plugin-manager.dtsi(TX2i)
An example of config#3 with 2x USB3.0 and 3x1 PCIe in hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts.

       gpio@2200000 {
		sdmmc-wake-support-input {
			status = "okay";
		};

		sdmmc-wake-support-output {
			status = "okay";
		};
		pcie0_lane2_mux {
			status = "okay"; //This is for switch from usb3.0 to x1 PCIe  on M.2.
		};
	};


	pcie-controller@10003000 {
		pci@1,0 {
			nvidia,num-lanes = <2>;
			nvidia,disable-clock-request;
			status = "okay";
		};
		pci@2,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
		pci@3,0 {
			nvidia,num-lanes = <1>;
			status = "okay";
		};
	};

        xhci@3530000 {
		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(2)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>,
			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(2)>;
		phy-names = "utmi-0", "utmi-1", "utmi-2", "usb3-1", "usb3-2";
	};

	pinctrl@3520000 {
	    pinmux {
		usb3-std-A-port2 {
			nvidia,lanes = "usb3-1";
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		usb3-std-A-port3 {
			nvidia,lanes = "usb3-2";
			nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
			status = "okay";
		};
		e3325-usb3-std-A-HS {
                    status = "okay"; //This is usb2.0 port on M.2
		};
	};
      };
      

Please remember to change odmdata in p2771-0000.conf.common. It is still a required steps.

USB3 OTG cable design

Certain cables on market violate USB3.0/USB3.1 spec. Please follow below steps to check your cables:

1) Pin No.10(MicB_SSRX+) on USB 3.0 Micro B plug(Male) side, as shown in USB 3.0 Micro B plug.png.
2) Pin No.6(StdA_SSRX+) on USB 3.0 Standard-A receptacle(Female) side, as shown in USB 3.0 Standard-A receptacle.png.
If the Tx/Rx signal are routed correctly, they should be short.
USB 3.0 Micro B plug.png
USB 3.0 Standard-A receptacle.png

For more details, please refer to below sections of USB3.1 spec:

- Figure 5-13. USB 3.1 Micro-B and Micro-A Plug Interface Dimensions
- Figure 5-1. USB 3.1 Standard-A Receptacle Interface Dimensions
- Table 5-4. USB 3.1 Micro-B Connector Pin Assignments
- Table 5-2. USB 3.1 Standard-A Connector Pin Assignments 

Discussion Thread

https://devtalk.nvidia.com/default/topic/1030635/jetson-tx2/tx2-config-4-for-usb-lane-mapping/post/5259826/#5259826

https://devtalk.nvidia.com/default/topic/1029899