Difference between revisions of "Minnowboard:MinnowMax"
(adding board layouts) |
(initial addition of the Linux GPIO pin mapping) |
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===== Layout ===== | ===== Layout ===== | ||
{| width="85%" style="text-align:center;" | {| width="85%" style="text-align:center;" | ||
− | ! width=" | + | ! width="20%" | Description |
! width="20%" | Name | ! width="20%" | Name | ||
! width="5%" | Pin | ! width="5%" | Pin | ||
+ | ! width="5%" | Linux GPIO Pin | ||
+ | ! width="5%" | Linux GPIO Pin | ||
! width="5%" | Pin | ! width="5%" | Pin | ||
! width="20%" | Name | ! width="20%" | Name | ||
− | ! width=" | + | ! width="20%" | Description |
|- | |- | ||
| Ground | | Ground | ||
| Gnd | | Gnd | ||
− | | style="border-style: solid; border-width: 1px;text-align:center;" | 1 | + | | style="border-style: solid; border-width: 1px;text-align:center;" | 1 |
+ | | colspan=2 | | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 2 | | style="border-style: solid; border-width: 1px;text-align:center;" | 2 | ||
| Gnd | | Gnd | ||
Line 174: | Line 177: | ||
| VCC | | VCC | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 3 | | style="border-style: solid; border-width: 1px;text-align:center;" | 3 | ||
+ | | colspan=2 | | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 4 | | style="border-style: solid; border-width: 1px;text-align:center;" | 4 | ||
| +3V3 | | +3V3 | ||
Line 180: | Line 184: | ||
| SPI Chip Select 1 | | SPI Chip Select 1 | ||
| GPIO_SPI_CS# | | GPIO_SPI_CS# | ||
− | | style="border-style: solid; border-width: 1px;text-align:center;" | 5 | + | | style="border-style: solid; border-width: 1px;text-align:center;" | 5 |
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 6 | | style="border-style: solid; border-width: 1px;text-align:center;" | 6 | ||
| GPIO_UART1_TXD | | GPIO_UART1_TXD | ||
Line 187: | Line 193: | ||
| Master In / Slave Out | | Master In / Slave Out | ||
| GPIO_SPI_MISO | | GPIO_SPI_MISO | ||
− | | style="border-style: solid; border-width: 1px;text-align:center;" | 7 | + | | style="border-style: solid; border-width: 1px;text-align:center;" | 7 |
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 8 | | style="border-style: solid; border-width: 1px;text-align:center;" | 8 | ||
| GPIO_UART1_RXD | | GPIO_UART1_RXD | ||
Line 194: | Line 202: | ||
| Master Out / Slave In | | Master Out / Slave In | ||
| GPIO_SPI_MOSI | | GPIO_SPI_MOSI | ||
− | | style="border-style: solid; border-width: 1px;text-align:center;" | 9 | + | | style="border-style: solid; border-width: 1px;text-align:center;" | 9 |
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 227 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 10 | | style="border-style: solid; border-width: 1px;text-align:center;" | 10 | ||
| GPIO_UART1_CTS | | GPIO_UART1_CTS | ||
Line 202: | Line 212: | ||
| GPIO_SPI_CLK | | GPIO_SPI_CLK | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 11 | | style="border-style: solid; border-width: 1px;text-align:center;" | 11 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 226 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 12 | | style="border-style: solid; border-width: 1px;text-align:center;" | 12 | ||
| GPIO_UART1_RTS | | GPIO_UART1_RTS | ||
Line 209: | Line 221: | ||
| GPIO_I2C_SCL | | GPIO_I2C_SCL | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 13 | | style="border-style: solid; border-width: 1px;text-align:center;" | 13 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 216 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 14 | | style="border-style: solid; border-width: 1px;text-align:center;" | 14 | ||
| GPIO_I2S_CLK | | GPIO_I2S_CLK | ||
Line 216: | Line 230: | ||
| GPIO_I2C_SDA | | GPIO_I2C_SDA | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 15 | | style="border-style: solid; border-width: 1px;text-align:center;" | 15 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 217 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 16 | | style="border-style: solid; border-width: 1px;text-align:center;" | 16 | ||
| GPIO_I2S_FRM | | GPIO_I2S_FRM | ||
Line 223: | Line 239: | ||
| GPIO_UART2_TXD | | GPIO_UART2_TXD | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 17 | | style="border-style: solid; border-width: 1px;text-align:center;" | 17 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 219 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 18 | | style="border-style: solid; border-width: 1px;text-align:center;" | 18 | ||
| GPIO_I2S_DO | | GPIO_I2S_DO | ||
Line 230: | Line 248: | ||
| GPIO_UART2_RXD | | GPIO_UART2_RXD | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 19 | | style="border-style: solid; border-width: 1px;text-align:center;" | 19 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | - | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 218 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 20 | | style="border-style: solid; border-width: 1px;text-align:center;" | 20 | ||
| GPIO_I2S_DI | | GPIO_I2S_DI | ||
Line 237: | Line 257: | ||
| GPIO_S5_0 | | GPIO_S5_0 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 21 | | style="border-style: solid; border-width: 1px;text-align:center;" | 21 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 82 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 248 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 22 | | style="border-style: solid; border-width: 1px;text-align:center;" | 22 | ||
| GPIO_PWM0 | | GPIO_PWM0 | ||
Line 244: | Line 266: | ||
| GPIO_S5_1 | | GPIO_S5_1 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 23 | | style="border-style: solid; border-width: 1px;text-align:center;" | 23 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 83 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 249 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 24 | | style="border-style: solid; border-width: 1px;text-align:center;" | 24 | ||
| GPIO_PWM1 | | GPIO_PWM1 | ||
Line 251: | Line 275: | ||
| GPIO_S5_4 | | GPIO_S5_4 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 25 | | style="border-style: solid; border-width: 1px;text-align:center;" | 25 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 84 | ||
+ | | style="border-style: solid; border-width: 1px;text-align:center;" | 208 | ||
| style="border-style: solid; border-width: 1px;text-align:center;" | 26 | | style="border-style: solid; border-width: 1px;text-align:center;" | 26 | ||
| GPIO_IBL_8254 | | GPIO_IBL_8254 |
Revision as of 16:21, 8 July 2014
Category | Feature |
---|---|
Core Logic |
|
Integrated Intel® HD Graphics With Open Source hardware-accelerated drivers for Linux OS | |
Memory |
|
8 MB SPI Flash System Firmware Memory | |
Video | Intel® HD Graphics HDMI (micro HDMI connector) |
Audio | Digital via HDMI |
Analog To be available separately via MinnowBoard MAX Lure (sold separately) | |
I/O | 1 – Micro SDSDIO |
1 – SATA2 3Gb/sec | |
1 – USB 3.0 (host) | |
1 – USB 2.0 (host) | |
1 – Serial debug via FTDI cable (sold separately) | |
10/100/1000 Ethernet RJ-45 connector | |
Experimenter Features |
8 – Buffered GPIO pins 2 pins support PWM |
I2C & SPI bus | |
System Firmware Flash Programming Header | |
Board Dimensions | 99 x 74mm (2.9 x 3.9in) |
Temperature Range | 0 – 70 deg C Contact CirtcuitCo for industrial temp range needs |
Power | 5V DC Sold separately in configurations appropriate to your region |
Operating Systems |
|
System Boot Firmware | UEFI Firmware |
Coreboot (in development) | |
Note: These features may be subject to change without notice. Hardware design files will be made available shortly after the board enters final production. Current estimate of public availability is June 2014. |
Contents
Resources
Hardware Notes
Board Layout
Power Plug
The Minnowboard Max uses a 5.5 x 2.1mm barrel 5V power plug, and if bundled will ship with a 2.5A power supply. It is a Center Positive power supply, indicating that the center (tip) of the output plug is positive (+), the outer barrel is negative (-). |
Serial Console
The serial console port uses a 3.3v FTDI serial cable with a 6-pin connector. This is a reasonably common cable, also used on the Arduino Pro, Arduino Pro Mini and Arduino Lilypad.
|
A0: |
A1: |
HDMI
The MinnowMax uses a Type D micro-HDMI connector. This is a standard port, for which cables and adapters can be readily picked up from most electronics stores
Low Speed Expansion (Top)
*** THIS IS PRE-PRODUCTION INFORMATION AND MAY BE SUBJECT TO CHANGE BEFORE PRODUCTION SHIPPING ***
The low speed connector uses 0.1" (2.54 mm) Male header pins in a 2 x 13 array, for a total of 26 pins. Pin 1 is the in the row closest to the power connector, and closest to the board edge.
Layout
Description | Name | Pin | Linux GPIO Pin | Linux GPIO Pin | Pin | Name | Description |
---|---|---|---|---|---|---|---|
Ground | Gnd | 1 | 2 | Gnd | Ground | ||
+5V Power | VCC | 3 | 4 | +3V3 | + 3.3V Power | ||
SPI Chip Select 1 | GPIO_SPI_CS# | 5 | - | - | 6 | GPIO_UART1_TXD | UART Transmit |
Master In / Slave Out | GPIO_SPI_MISO | 7 | - | - | 8 | GPIO_UART1_RXD | UART Receive |
Master Out / Slave In | GPIO_SPI_MOSI | 9 | - | 227 | 10 | GPIO_UART1_CTS | CTS / GPIO |
SPI Clock | GPIO_SPI_CLK | 11 | - | 226 | 12 | GPIO_UART1_RTS | RTS / GPIO |
Clock / GPIO | GPIO_I2C_SCL | 13 | - | 216 | 14 | GPIO_I2S_CLK | Clock / GPIO |
Data / GPIO | GPIO_I2C_SDA | 15 | - | 217 | 16 | GPIO_I2S_FRM | Frame / GPIO |
UART Transmit / GPIO | GPIO_UART2_TXD | 17 | - | 219 | 18 | GPIO_I2S_DO | Data Out / GPIO |
UART Receive / GPIO | GPIO_UART2_RXD | 19 | - | 218 | 20 | GPIO_I2S_DI | Data In / GPIO |
GPIO / Wakeup | GPIO_S5_0 | 21 | 82 | 248 | 22 | GPIO_PWM0 | PWM / GPIO |
GPIO / Wakeup | GPIO_S5_1 | 23 | 83 | 249 | 24 | GPIO_PWM1 | PWM / GPIO |
GPIO / Wakeup | GPIO_S5_4 | 25 | 84 | 208 | 26 | GPIO_IBL_8254 | Timer / GPIO |
NOTE: Pins 5-26 are shown above with their PRIMARY configuration, any pin may be switched to being a generic GPIO as well. This would give a total of 22 GPIOs, with two of those being PWM capable.
High Speed Expansion (Bottom)
*** THIS IS PRE-PRODUCTION INFORMATION AND MAY BE SUBJECT TO CHANGE BEFORE PRODUCTION SHIPPING ***
The High speed connector uses a TE Connectivity compatible 60-pin header. The generally recommended header is the 3-5177986-2, or the 60POS .8MM FH 8H GOLD part that rises 7.85mm, allowing for 3/8" standoffs at the corners to be used to attach the lure to the minnowboard.
Link to connector used: http://www.digikey.com/product-detail/en/5177985-2/A99190CT-ND/1894007. mating connectors are listed at the bottom but include:
- A99196DKR-ND - CONN PLUG 60POS .8MM FH 5H GOLD
- A115336-ND - CONN PLUG 60POS DL BRD/BRD VERT
- 5179030-2-ND - CONN PLUG 60POS FH .8MM BRD-BRD
- 5177984-2-ND - CONN PLUG 60POS VERT FH .8MM
- A99215CT-ND - CONN PLUG 60POS .8MM FH 8H GOLD <-- Recommended connector
- A99209CT-ND - CONN PLUG 60POS .8MM FH 7H GOLD
- A99203CT-ND - CONN PLUG 60POS .8MM FH 6H GOLD
- A99196CT-ND - CONN PLUG 60POS .8MM FH 5H GOLD
- A99215TR-ND - CONN PLUG 60POS .8MM FH 8H GOLD
- A99209TR-ND - CONN PLUG 60POS .8MM FH 7H GOLD
Layout
Description | Pin | Pin | Description |
---|---|---|---|
Ground | 1 | 2 | Ground |
mSATA_TX_P | 3 | 4 | mSATA_RX_P |
mSATA_TX_N | 5 | 6 | mSATA_RX_N |
+5V SB | 7 | 8 | +5V SB |
mPCIE_REFCLK_P | 9 | 10 | USB_HOST_DP |
mPCIE_REFCLK_N | 11 | 12 | USB_HOST_DN |
Ground | 13 | 14 | Ground |
mPCIE_TX_P | 15 | 16 | mPCIE_RX_P |
mPCIE_TX_N | 17 | 18 | mPCIE_RX_N |
+5V SB | 19 | 20 | +5V SB |
EXP_I2C_SCL | 21 | 22 | mPCIE_WAKEB |
EXP_I2C_SDA | 23 | 24 | mPCIe_CLKREQ3_B |
Ground | 25 | 26 | Ground |
EXP_GPIO1 | 27 | 28 | EXP_GPIO3 |
EXP_GPIO2 | 29 | 30 | EXP_GPIO4 |
+5V SB | 31 | 32 | +5V SB |
XDP_H_OBSDATA_A1 | 33 | 34 | XDP_H_OBSDATA_A0 |
XDP_H_OBSDATA_A2 | 35 | 36 | XDP_H_OBSDATA_A3 |
Ground | 37 | 38 | Ground |
XDP_H_PRDYB | 39 | 40 | XDP_H_PREQB_PB |
PMC_RSMRST | 41 | 42 | FP_PWRBTN |
+5V SB | 43 | 44 | +5V SB |
PMC_CORE_PWROK | 45 | 46 | PMC_RSTBTN |
PMC_PLTRST_R_V1P8 | 47 | 48 | ILB_RTC_TESTB |
Ground | 49 | 50 | Ground |
51 | 52 | XDP_H_TRSTB | |
53 | 54 | XDP_H_TCK | |
+V1P8A | 55 | 56 | XDP_H_TMS |
+V1P8A | 57 | 58 | XDP_H_TDI |
Ground | 59 | 60 | Ground |
SPI Header to Firmware flashing J1
*** THIS IS PRE-PRODUCTION INFORMATION AND MAY BE SUBJECT TO CHANGE BEFORE PRODUCTION SHIPPING ***
This is a pinned out port to allow for external flashing of the boot spi. Dediprog and Flyswatter devices have been tested and verified to work with this.
Layout
Description | Pin | Pin | Description |
---|---|---|---|
DDP_1V8 | 1 | 2 | Ground |
DDP_SPI_CS | 3 | 4 | DDP_SPI_CLK |
DDP_SPI_MISO | 5 | 6 | DDP_SPI_MOSI |
7 | 8 | DDP_IO3L |
Power Connection J2 (SIP2_FAN)
*** THIS IS PRE-PRODUCTION INFORMATION AND MAY BE SUBJECT TO CHANGE BEFORE PRODUCTION SHIPPING ***
This is a 5V 2-pin pin out originally intended to be used for a CPU fan. The single core (E3815) and the dual core (E3825) however use passive heat sinks, and thus do not, under normal circumstances, need a fan. It is theoretically possible to pull upwards of 1A through this port, however you should refer to the released schematics to verify that number before attempting to use this for anything.
NOTE: This is not populated on the Single, or Dual core boards. This can be populated if needed, and will provide the above power
Layout
Description | Pin | Pin | Description |
---|---|---|---|
Ground | 1 | 2 | +5VSB |
Switch Jumper J5
*** THIS IS PRE-PRODUCTION INFORMATION AND MAY BE SUBJECT TO CHANGE BEFORE PRODUCTION SHIPPING ***
This pin is intended to allow for power toggling via a remote switch or relay. It is fundamentally no different than pressing SW1, and behaves identically.
NOTE: This is not populated, by default.
Layout
Description | Pin | Pin | Description |
---|---|---|---|
+5VSB | 1 | 2 | Ground |
SATA LED J6
*** THIS IS PRE-PRODUCTION INFORMATION AND MAY BE SUBJECT TO CHANGE BEFORE PRODUCTION SHIPPING ***
This is intended to be an HD LED type activity indicator, shorting the pins enables, leaving it out disables.
NOTE: This is not populated, by default.
Layout
Description | Pin | Pin | Description |
---|---|---|---|
1 | 2 | +V1P8S |
Known Issues
MinnowBoard-MAX Open Bugs (Bugzilla)
- Bugzilla:
We currently use the YoctoProject Bugzilla instance at http://bugzilla.yoctoproject.org - Bug Triage link can be found at: https://wiki.yoctoproject.org/wiki/Minnow_Bug_Triage
A1
Hardware
USB
There is a potential issue when using a powered USB Hub. If the hub, erroneously, provides power over the USB 3 or USB 2 input connector, the MinnowBoard MAX will use that as power. This is in violation of the USB spec, and will be rectified in a later revision of the MinnowBoard MAX.
Hubs known to cause this:
- iXCC 7 Port USB 3.0 Hub
It is suggested that you check powered USB hubs to confirm that they do not provide power back to the board, as described, and if a hub is found to do this, please report it here. A hub found to be doing this should be used without being externally powered if used at all.
Firmware
See the bug list, linked above.
Unknown
Monitors
There is an issue with regards to some monitors not being able to display from the MinnowBoard MAX. Most monitors seem to be fine, but some will either completely not show a display (even at firmware boot-up) or may only show a display after the operating system is booting.
This is being investigated.