Difference between revisions of "OpenOCD PandaBoard"
| Line 10: | Line 10: | ||
changing ''-coreid 0'' to ''-coreid 1''. At present it is not possible to connect to both Cortex-A9 cores simultaneously. | changing ''-coreid 0'' to ''-coreid 1''. At present it is not possible to connect to both Cortex-A9 cores simultaneously. | ||
| − | === Working Items === | + | ==== Working Items ==== |
* halt, single-step, resume | * halt, single-step, resume | ||
* breakpoints and watchpoints | * breakpoints and watchpoints | ||
| Line 18: | Line 18: | ||
All memory accesses (including md/mw commands and disassembly) execute through the debug AHB on the L3 interconnect; resources on the L2 interconnect currently can not be accessed. This includes ROM, local PRCM, and anything in the Cortex-A9 "private memory region" (snoop-control unit, global interrupt controller, timers and watchdogs). | All memory accesses (including md/mw commands and disassembly) execute through the debug AHB on the L3 interconnect; resources on the L2 interconnect currently can not be accessed. This includes ROM, local PRCM, and anything in the Cortex-A9 "private memory region" (snoop-control unit, global interrupt controller, timers and watchdogs). | ||
| − | === Non-Working Items === | + | ==== Non-Working Items ==== |
* debugging A9 cores simultaneously | * debugging A9 cores simultaneously | ||
* accessing L2 memory resources | * accessing L2 memory resources | ||
* unify a8/a9 code | * unify a8/a9 code | ||
| − | === Debug clocking === | + | ==== Debug clocking ==== |
The debugger may not be able to access the A9 processor cores due to an issue with omap4430 clocking. If your debugger can identify JTAG devices, e.g.: | The debugger may not be able to access the A9 processor cores due to an issue with omap4430 clocking. If your debugger can identify JTAG devices, e.g.: | ||
Info : 375 316 core.c:948 jtag_examine_chain_display(): JTAG tap: omap4430.jrc tap/device found: 0x3b95c02f (mfg: 0x017, part: 0xb95c, ver: 0x3) | Info : 375 316 core.c:948 jtag_examine_chain_display(): JTAG tap: omap4430.jrc tap/device found: 0x3b95c02f (mfg: 0x017, part: 0xb95c, ver: 0x3) | ||
Revision as of 10:45, 19 April 2012
OpenOCD
OpenOCD mainline includes preliminary support for Cortex-A9 and Pandaboard. See the OpenOCD homepage for instructions to checkout and build from source.
Invoke OpenOCD as:
openocd -f tcl/interface/flyswatter.cfg -f tcl/board/ti_pandaboard.cfg
replacing flyswatter.cfg with the appropriate config for your JTAG hardware.
The default configuration exposes 3 targets: one Cortex-A9 (core 0) and two Cortex-M3 cores. To connect to the second Cortex-A9 core, edit the following line in tcl/target/omap4430.cfg:
target create $_TARGETNAME cortex_a9 -chain-position $_CHIPNAME.dap -coreid 0
changing -coreid 0 to -coreid 1. At present it is not possible to connect to both Cortex-A9 cores simultaneously.
Working Items
- halt, single-step, resume
- breakpoints and watchpoints
- reading/writing memory
- inspecting core/register state
All memory accesses (including md/mw commands and disassembly) execute through the debug AHB on the L3 interconnect; resources on the L2 interconnect currently can not be accessed. This includes ROM, local PRCM, and anything in the Cortex-A9 "private memory region" (snoop-control unit, global interrupt controller, timers and watchdogs).
Non-Working Items
- debugging A9 cores simultaneously
- accessing L2 memory resources
- unify a8/a9 code
Debug clocking
The debugger may not be able to access the A9 processor cores due to an issue with omap4430 clocking. If your debugger can identify JTAG devices, e.g.:
Info : 375 316 core.c:948 jtag_examine_chain_display(): JTAG tap: omap4430.jrc tap/device found: 0x3b95c02f (mfg: 0x017, part: 0xb95c, ver: 0x3)
but no Cortex-A9 target appears, you are probably running into this issue. Verify by connecting the debugger with no SD card inserted: if it now works, you're hitting this issue.
The current x-loader mainline includes a workaround.
