Difference between revisions of "OpenOCD PandaBoard"

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== Known Issues ==
 
== Known Issues ==
  
=== Memory Access ===
+
==== Memory Access ====
 
All memory accesses (including md/mw commands and disassembly) execute through the debug AHB on the L3 interconnect; resources on the L2 interconnect currently can not be accessed.  This includes ROM, local PRCM, and anything in the Cortex-A9 "private memory region" (snoop-control unit, global interrupt controller, timers and watchdogs).
 
All memory accesses (including md/mw commands and disassembly) execute through the debug AHB on the L3 interconnect; resources on the L2 interconnect currently can not be accessed.  This includes ROM, local PRCM, and anything in the Cortex-A9 "private memory region" (snoop-control unit, global interrupt controller, timers and watchdogs).
  
=== SMP Support ===
+
==== SMP Support ===
  
 
debugging A9 cores simultaneously is currrently not supported
 
debugging A9 cores simultaneously is currrently not supported
  
=== Debug clocking ===
+
==== Debug clocking ====
 
The debugger may not be able to access the A9 processor cores due to an issue with omap4430 clocking.  If your debugger can identify JTAG devices, e.g.:
 
The debugger may not be able to access the A9 processor cores due to an issue with omap4430 clocking.  If your debugger can identify JTAG devices, e.g.:
 
  Info : 375 316 core.c:948 jtag_examine_chain_display(): JTAG tap: omap4430.jrc tap/device found: 0x3b95c02f (mfg: 0x017, part: 0xb95c, ver: 0x3)
 
  Info : 375 316 core.c:948 jtag_examine_chain_display(): JTAG tap: omap4430.jrc tap/device found: 0x3b95c02f (mfg: 0x017, part: 0xb95c, ver: 0x3)

Revision as of 11:12, 19 April 2012

Introduction

OpenOCD mainline includes preliminary support for Cortex-A9 and Pandaboard. See the Compiling_OpenOCD for instructions to checkout and build from source, or visit OpenOCD homepage.

JTAG Hardware HowTos

Known Issues

Memory Access

All memory accesses (including md/mw commands and disassembly) execute through the debug AHB on the L3 interconnect; resources on the L2 interconnect currently can not be accessed. This includes ROM, local PRCM, and anything in the Cortex-A9 "private memory region" (snoop-control unit, global interrupt controller, timers and watchdogs).

= SMP Support

debugging A9 cores simultaneously is currrently not supported

Debug clocking

The debugger may not be able to access the A9 processor cores due to an issue with omap4430 clocking. If your debugger can identify JTAG devices, e.g.:

Info : 375 316 core.c:948 jtag_examine_chain_display(): JTAG tap: omap4430.jrc tap/device found: 0x3b95c02f (mfg: 0x017, part: 0xb95c, ver: 0x3)

but no Cortex-A9 target appears, you are probably running into this issue. Verify by connecting the debugger with no SD card inserted: if it now works, you're hitting this issue.

The current x-loader mainline includes a workaround.