Difference between revisions of "The Undocumented Pi"
(→SoC: Clock hierarchy) |
(→BCM2711: Clock manager update) |
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===BCM2711=== | ===BCM2711=== | ||
| − | The BCM2711 does not have PLLH. | + | The BCM2711 does not have PLLH. It also lacks the following clock muxes: |
| + | |||
| + | * GNRIC | ||
| + | * CCP2 | ||
| + | * HSM (controlled through other registers?) | ||
| + | * SLIM | ||
| + | * SDC (controlled through other registers?) | ||
| + | * ARM (controlled through other registers?) | ||
| + | * AVEO | ||
| + | |||
| + | It has the following extra clock mux registers (their names are just made up, because there is no official documentation): | ||
| + | |||
| + | {|class="wikitable" | ||
| + | ! name !! address !! type || width || mask || reset || description | ||
| + | |- | ||
| + | | <code>CM_HEVCCTL</code> ||align="right"| <code>0x7e1011c8</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_HEVCDIV</code> ||align="right"| <code>0x7e1011cc</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_EMMC2CTL</code> ||align="right"| <code>0x7e1011d0</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_EMMC2DIV</code> ||align="right"| <code>0x7e1011d4</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_GENET250CTL</code> ||align="right"| <code>0x7e1011e8</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_GENET250DIV</code> ||align="right"| <code>0x7e1011ec</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_STB27CTL</code> ||align="right"| <code>0x7e1011f0</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_STB27DIV</code> ||align="right"| <code>0x7e1011f4</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_STB108CTL</code> ||align="right"| <code>0x7e101200</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_STB108DIV</code> ||align="right"| <code>0x7e101204</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_PIXBVBCTL</code> ||align="right"| <code>0x7e101208</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_PIXBVBDIV</code> ||align="right"| <code>0x7e10120c</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_GENET125CTL</code> ||align="right"| <code>0x7e101210</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_GENET125DIV</code> ||align="right"| <code>0x7e101214</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_M2MCCTL</code> ||align="right"| <code>0x7e10122c</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_M2MCDIV</code> ||align="right"| <code>0x7e101230</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_USBXHCICTL</code> ||align="right"| <code>0x7e10123c</code> ||align="center"| RW ||align="right"| 20 ||align="right"| <code>???</code> ||align="right"| <code>0000000000</code> || | ||
| + | |- | ||
| + | | <code>CM_USBXHCIDIV</code> ||align="right"| <code>0x7e101240</code> ||align="center"| RW ||align="right"| 24 ||align="right"| <code>0x00ffffff</code> ||align="right"| <code>0000000000</code> || | ||
| + | |} | ||
| + | |||
The VCE block was apparently removed, but there is now a HEVC block. | The VCE block was apparently removed, but there is now a HEVC block. | ||
Revision as of 00:33, 4 March 2020
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Hardware
SoC
There is a nicely ordered table with all BCM2835_registers as found in the GPU code published by Broadcom. Unfortunately, the table does not quite match the SoC in the Raspberry Pi, but it's a good start. The sections below should serve as a companion to that table.
Clocks
BCM283x
There is a VCE block to accelerate video encoding/decoding. No documentation AFAIK.
BCM2711
The BCM2711 does not have PLLH. It also lacks the following clock muxes:
- GNRIC
- CCP2
- HSM (controlled through other registers?)
- SLIM
- SDC (controlled through other registers?)
- ARM (controlled through other registers?)
- AVEO
It has the following extra clock mux registers (their names are just made up, because there is no official documentation):
| name | address | type | width | mask | reset | description |
|---|---|---|---|---|---|---|
CM_HEVCCTL |
0x7e1011c8 |
RW | 20 | ??? |
0000000000 |
|
CM_HEVCDIV |
0x7e1011cc |
RW | 24 | 0x00ffffff |
0000000000 |
|
CM_EMMC2CTL |
0x7e1011d0 |
RW | 20 | ??? |
0000000000 |
|
CM_EMMC2DIV |
0x7e1011d4 |
RW | 24 | 0x00ffffff |
0000000000 |
|
CM_GENET250CTL |
0x7e1011e8 |
RW | 20 | ??? |
0000000000 |
|
CM_GENET250DIV |
0x7e1011ec |
RW | 24 | 0x00ffffff |
0000000000 |
|
CM_STB27CTL |
0x7e1011f0 |
RW | 20 | ??? |
0000000000 |
|
CM_STB27DIV |
0x7e1011f4 |
RW | 24 | 0x00ffffff |
0000000000 |
|
CM_STB108CTL |
0x7e101200 |
RW | 20 | ??? |
0000000000 |
|
CM_STB108DIV |
0x7e101204 |
RW | 24 | 0x00ffffff |
0000000000 |
|
CM_PIXBVBCTL |
0x7e101208 |
RW | 20 | ??? |
0000000000 |
|
CM_PIXBVBDIV |
0x7e10120c |
RW | 24 | 0x00ffffff |
0000000000 |
|
CM_GENET125CTL |
0x7e101210 |
RW | 20 | ??? |
0000000000 |
|
CM_GENET125DIV |
0x7e101214 |
RW | 24 | 0x00ffffff |
0000000000 |
|
CM_M2MCCTL |
0x7e10122c |
RW | 20 | ??? |
0000000000 |
|
CM_M2MCDIV |
0x7e101230 |
RW | 24 | 0x00ffffff |
0000000000 |
|
CM_USBXHCICTL |
0x7e10123c |
RW | 20 | ??? |
0000000000 |
|
CM_USBXHCIDIV |
0x7e101240 |
RW | 24 | 0x00ffffff |
0000000000 |
The VCE block was apparently removed, but there is now a HEVC block.
PMIC
The BCM2835 chip has an on-chip SMPS and an LDO for the LPDDR2 memory chip. RPi2 and RPi3 B use custom circuitry made of discrete components to do the power-up sequencing, including an NCP6343 chip (datasheet) at I²C address 0x1c. The RPi 3B+ and RPi 4B boards contain a MaxLinear MxL7704 (datasheet) at address 0x1d.
The PMIC is always on the system I²C bus (I2C8 on RPi4, I2C0 on all other devices).
See also this very informative blog post by James Adams.
Boot ROM
Firmware
Abbreviations
- CM
- Clock Manager
- HSM
- HDMI State Machine
- OTP
- One-Time Programmable (memory)
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