Requirements for SD/MMC and SPI

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Revision as of 31 July 2016 at 13:59.
This is the thread's initial revision.

"In essence, the SD/MMC committee have caused a bit of trouble, here, but it may be best to trust their experience in that SD/MMC Cards have probably not, for some considerable time, been actually using SPI mode, but have been offering the 2, 4 (and now 8) lane capability for a long, long time."

By 2-bit, do we mean the SD/MMC mode where data is transferred one bit at a time over either command or data lines? Just to get the terminology right, I believe SD calls it 1-bit SD.

    05:59, 31 July 2016