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The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O. These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.

PRUs are programmed in Assembly, with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200Mhz, a single cycle will always take 5ns (nanoseconds) to execute.

This is a Work In Progress

Available PRU Resources

Click here for a full list of register mappings.


8KB program memory
Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.
Enhanced GPIO (EGPIO)
High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.
pr1_pru_0_pru_r30[15:0] (PRU0 Register R30 Outputs)
pr1_pru_0_pru_r31[16:0] (PRU0 Register R31 Inputs)
pr1_pru_1_pru_r30[15:0] (PRU1 Register R30 Outputs)
pr1_pru_1_pru_r31[16:0] (PRU1 Register R31 Inputs)
Hardware capture modes
Serial 28-bit shift in and out.
Parallel 16-bit capture on clock.
MII standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).
A 32-bit multiply and accumulate unit (MAC)
Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).
8KB data memory
Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.
One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.
Open Core Protocol (OCP) master port
Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.

Shared Between PRUs

Scratch pad
3 banks of 30 32-bit registers (total 90 32-bit registers).
Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.
12KB data memory
Accessed over the 32-but bus, not single-cycle.

Local Peripherals

Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.

Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.

Enhanced Capture Model (eCAP)
Industrial Ethernet Peripheral (IEP)
Universal Asynchronous Receiver/Transmitter (UART0)
Used to perform serial data transmission to the TL16C550 industry standard.
16-bit FIFO receive and transmit buffers + per byte error status.
Can generate Interrupt requests for the PRUSS Interrupt Controller.
Can generate DMA requests for the EDMA SoC DMA controller.
Maximum transmission speed of 192MHz (192Mbps - 24MB/s).


Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.

The following lists will expose all possible communication approaches for each likely scenario.

For communication via interrupts, please first read the section on the PRUSSv2 Interrupt Controller.

Click here for a full list of PRUSS Interrupts.

The current PRU loader uses UIO, but this ideally should be replaced with remoteproc rather than poking at the registers from userspace.

PRU to Host (PRU to ARM Cortex-A8)

Host to PRU (ARM Cortex-A8 to PRU)


Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively. By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.

To configure

PRU to external peripherals

External peripherals to PRU

PRU to internal peripherals

Internal peripherals to PRU

Loading a PRU Program

Beaglebone PRU connections and modes:

PRU # R30(input) bit Pinmux Mode R31(output) bit Pinmux Mode Header Location/Pin Name ZCZ BallName
0 0 Mode_6 0 Mode_5 P9_31-SPI1_SCLK mcasp0_aclkx
0 1 Mode_6 1 Mode_5 P9_31-SPI1_D0 mcasp0_fsx
0 2 Mode_6 2 Mode_5 P9_30-SPI1_D1 mcasp0_axr0
0 3 Mode_6 3 Mode_5 P9_28-SPI1_CS0 mcasp0_ahclkr
0 4 Mode_6 4 Mode_5 P9_42 (*see note1 below) mcasp0_aclkr
0 5 Mode_6 5 Mode_5 P9_27-GPIO3_19 mcasp0_fsr
0 6 Mode_6 6 Mode_5 P9_41(*see note2 below) mcasp0_axr1
0 7 Mode_6 7 Mode_5 P9_25-GPIO3_21 mcasp0_ahclkx
0 N/A 14 Mode_6 P8_12-GPIO1_12 gpmc_ad12
0 N/A 15 Mode_6 P8_11-GPIO1_13 gpmc_ad9
0 14 Mode_6 N/A P8_16-GPIO1_14 gpmc_ad14
0 15 Mode_6 N/A P8_15-GPIO1_15 gpmc_ad15
1 0 Mode_6 0 Mode_5 P8_45-GPIO2_6 lcd_data0
1 1 Mode_6 1 Mode_5 P8_46-GPIO2_7 lcd_data1
1 2 Mode_6 2 Mode_5 P8_43-GPIO2_8 lcd_data2
1 3 Mode_6 3 Mode_5 P8_44-GPIO2_9 lcd_data3
1 4 Mode_6 4 Mode_5 P8_41-GPIO2_10 lcd_data4
1 5 Mode_6 5 Mode_5 P8_42-GPIO2_11 lcd_data5
1 6 Mode_6 6 Mode_5 P8_39-GPIO2_12 lcd_data6
1 7 Mode_6 7 Mode_5 P8_40-GPIO2_13 lcd_data7
1 8 Mode_6 8 Mode_5 P8_27-GPIO2_22 lcd_vsync
1 9 Mode_6 9 Mode_5 P8_29-GPIO2_23 lcd_hsync
1 10 Mode_6 10 Mode_5 P8_28-GPIO2_24 lcd_pclk
1 11 Mode_6 11 Mode_5 P8_30-GPIO2_25 lcd_ac_bias_en
1 12 Mode_6 12 Mode_5 P8_21-GPIO1_30 gpmc_csn1
1 13 Mode_6 13 Mode_5 P8_20-GPIO1_31 gpmc_csn2
1 16 Mode_6 N/A P9_26-UART1_RXD uart1_rxd
  • Note1*: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.
  • Note2*: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.


The documentation on the subsystem is here. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.